Semiconductor memory device

Abstract

A semiconductor memory device wherein, if an address-input buffer section 3 is arranged away from a central part of a memory chip 8, then a second address-latch circuit section 5 is arranged at a neighborhood of the address-input buffer section 3. By this means, the deterioration of the setup/hold characteristics in the address data IA[0-12] of the internal address signal due to coupling noise between wiring lines and the like can be prevented. A first address-latch circuit section 4 is arranged at a central part of the memory chip 8, so that delays in a bank-control signal for memory banks 2a to 2d and the like can be prevented. Further, if the address-input buffer section 3 is divided into a plurality of address-input buffers, for example, two buffers 3a and 3b, and arranged on the memory chip 8, then the second address-latch circuit section 5 is also divided into two address-latch circuits 5a and 5b, corresponding to the address-input buffers 3a and 3b, and the address-latch circuit 5a is arranged at a neighborhood of the address-input buffer 3a, and the address-latch circuit 5b is arranged at a neighborhood of the address-input buffer 3b.

Dependencies are inferred from the claim text.