Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array having a plurality of cores each of which has electrically rewritable nonvolatile memory cells and is divided into one or more cell blocks each of which forms a unit of data erasure;
• a core select circuit selecting an arbitrary number of cores from said plurality of cores for data writing/erasing;
• a data write circuit writing data into selected memory cells in a core selected by said core select circuit;
• a data erase circuit erasing data in a selected block in a core selected by said core select circuit;
• and
• a data read circuit reading data from memory cells in a core which is not selected by said core select circuit,
• the sequence in which, at the end of a write/erase operation, a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are reset being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.

A semiconductor memory device comprising:

• a memory cell array having a plurality of cores each of which has electrically rewritable nonvolatile memory cells and is divided into one or more cell blocks each of which forms a unit of data erasure;
• a core select circuit selecting an arbitrary number of cores from said plurality of cores for data writing/erasing;
• a data write circuit writing data into selected memory cells in a core selected by said core select circuit;
• a data erase circuit erasing data in a selected block in a core selected by said core select circuit;
• and
• a data read circuit reading data from memory cells in a core which is not selected by said core select circuit,
• the sequence in which, at the suspending of a write/erase operation, a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are reset being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.

A semiconductor memory device comprising:

• a memory cell array having a plurality of cores each of which has electrically rewritable nonvolatile memory cells and is divided into one or more cell blocks each of which forms a unit of data erasure;
• a core select circuit selecting an arbitrary number of cores from said plurality of cores for data writing/erasing;
• a data write circuit writing data into selected memory cells in a core selected by said core select circuit;
• a data erase circuit erasing data in a selected block in a core selected by said core select circuit;
• and
• a data read circuit reading data from memory cells in a core which is not selected by said core select circuit,
• the sequence in which, at the resuming of a write/erase operation which has been suspended, a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.

A semiconductor memory device comprising:

• a memory cell array having a plurality of cores each of which has electrically rewritable nonvolatile memory cells and is divided into one or more cell blocks each of which forms a unit of data erasure;
• a core select circuit selecting an arbitrary number of cores from said plurality of cores for data writing/erasing;
• a data write circuit writing data into selected memory cells in a core selected by said core select circuit;
• a data erase circuit erasing data in a selected block in a core selected by said core select circuit;
• and
• a data read circuit reading data from memory cells in a core which is not selected by said core select circuit,
• the sequence in which, at the start of a write/erase operation, a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur,
• the sequence in which, at the end of the write/erase operation, the command, the core select signal, and the busy signal are reset being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur,
• the sequence in which, at the suspending of the write/erase operation, the command, the core select signal, and the busy signal are reset being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur, and
• the sequence in which, at the resuming of the write/erase operation which has been suspended, the command, the core select signal, and the busy signal are set being set so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.