High speed memory array architecture

A method of reading a plurality of N data bits of a data burst comprising:

• storing said N data bits at respective memory locations in burst order such that a preceding data bits of said burst is electrically closer to a multiplexer than a next subsequent data bit of said burst;
• transferring said N data bits to said multiplexer;
• and,
• outputting said N data bits from said multiplexer in burst order.

A method of storing a plurality of data bits comprising:

• receiving first and second data bit values at first and second memory locations respectively;
• transferring said first and second data bit values to first and second multiplexer locations respectively;
• completing said transfer of said first bit value from said multiplexer prior to completing said transfer of said second bit value;
• and
• outputting said first bit value from said multiplexer prior to completing transfer of said second bit value.

A method of recovering data from a data quadrant of a memory integrated circuit comprising:

• receiving a data address from an external address source;
• concurrently reading a plurality of bits of data from a respective plurality of memory locations, said locations selected according to said address;
• storing said respective plurality of bits in a respective plurality of multiplexer input locations;
• outputting said respective plurality of bits from said respective multiplexer input locations in a particular time sequence such that a first bit output is a bit retrieved from one of said plurality of memory locations electrically closest to said respective buffer location.

A method of reading data from a memory integrated circuit comprising:

• receiving an address at an input of an address decoder;
• decoding said address within said address decoder;
• selecting a plurality of memory storage locations with said address decoder;
• receiving a plurality of data bits, one from each location of said plurality of locations respectively;
• defining an output order for said plurality of data bits, said output order defining the order of at least first and second data bits such that said first data bit travels a shorter electrical distance between said respective storage location and an output buffer than said second data bit travels between said respective storage location and said output buffer;
• sequentially outputting said plurality of data bits in said defined order.

A method of outputting data comprising:

• storing a first data bit in a first cell at a first location;
• storing a second data bit in a second cell at a second location;
• said second location being electrically farther from an output buffer than said first location;
• said first and second cells adapted to being logically defined by a single address;
• receiving said address at an address decoder;
• concurrently signaling said first and second cells according to said address;
• and
• outputting said first data bit from said output buffer and subsequently outputting said second data bit from said output buffer.

A memory integrated circuit device comprising:

• a multiplexer including a plurality of inputs for receiving data, said multiplexer adapted to output data in a particular chronological order such that data received at a first one of said plurality of inputs is output before data received at a last one of said plurality of inputs;
• a plurality of memory cells disposed at a respective plurality of different locations;
• and
• a plurality of connecting paths, each paths of said plurality having a characteristic electrical length, each said path switchingly connected between one of said plurality of cells and one of said plurality of multiplexer inputs, the path of said plurality having a shortest electrical length being switchingly connected to said first multiplexer input.

A memory integrated circuit device comprising:

• an address decoder circuit adapted to receive an address signal;
• first and second memory storage circuits adapted to store first and second data values respectively, each said memory storage circuit operatively connected to said address decoder circuit so as to receive from said address decoder circuit a respective select signal sent concurrently to both said first and second storage circuits;
• and
• a data output circuit operatively connected to said first and second memory storage circuits adapted to receive said first and second data values from said first and second memory storage circuits respectively, said data output circuit adapted to output said respective received data values, said data output circuit being electrically closer to said first memory storage circuit than said second memory storage circuit, said data output circuit adapted to output said first data value from said first memory storage circuit before outputting said second data value from said second memory storage circuit, whereby said first output may occur prior to said receipt of said second data value at said data output circuit.

A memory integrated circuit device comprising:

• an address decoder circuit;
• a memory bank including a first plurality of memory bit storage locations;
• a multiplexer including a second plurality of demux bit storage locations, said plurality of demux bit storage locations arranged according to a particular output order, said output order including a first output bit;
• a plurality of electrical connections, each including a sense amplifier and a conductive trace, each of said plurality of electrical connections operatively connecting a memory bit storage location of said first plurality to a respective demux storage location of said second plurality, each of said plurality of electrical connections having a characteristic electrical length;
• and
• an electrical connection of said plurality of electrically connections operatively connected to said first output bit having a characteristic electrical length no longer than the characteristic electrical length of any other electrical connection of said plurality of electrical connections.

A memory integrated circuit device comprising:

• means for receiving a memory address from an external address source;
• a plurality of memory bit storage locations, said locations corresponding to said memory address;
• means for decoding said memory address;
• means for retrieving a plurality of bits of data concurrently from said plurality of memory bit storage locations respectively according to said decoded address;
• means for outputting said plurality of bits serially in a particular order such that a first bit output of said plurality is a bit stored at one of said storage locations electrically closer to said outputting means than a subsequent bit of said plurality.