System and method for terminating lock-step sequences in a multiprocessor system
AssigneeIntel Corporation
InventorsRobert J. Miller, Edward A. McDonald
Life of this patent
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Abstract
There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.
Claims20
For use in a processing system containing a plurality of processors coupled to a main memory by a first common bus, a control circuit for perturbing a lock-step sequence of memory requests received from said processors, said control circuit comprising:
- a memory request generator adapted to be coupled to said first common bus for generating at least one memory request operable to terminate said lock-step sequence of memory requests.
A processing system comprising:
- a plurality of processors;
- a main memory;
- a memory control device coupled to said plurality of processors by a first common bus and to said main memory for receiving memory request from said plurality of processors and transferring data between said plurality of processors and said main memory;
- and
- a control circuit for perturbing a lock-step sequence of memory requests received from said processors, said control circuit comprising a memory request generator coupled to said first common bus for generating at least one memory request operable to terminate said lock-step sequence of memory requests.
In a processing system containing a plurality of processors coupled to a main memory by a first common bus, a method for perturbing a lock-step sequence of memory requests received from the processors, the method comprising the step of generating at least one memory request on the first common bus, the at least one memory request operable to terminate the lock-step sequence of memory requests.
Dependencies are inferred from the claim text.