Nonvolatile semiconductor memory device and method of detecting overerased cell

A nonvolatile semiconductor memory device comprising:

• a memory cell array including:
• a plurality of floating gate electric field effect transistors arranged in a matrix, each having a control gate, a drain and a source and being capable of electrically writing and erasing information, wherein a threshold voltage of each of the floating gate electric field effect transistors in a written state is higher than a threshold voltage of each of the floating gate electric field effect transistors in an erased state,
• a plurality of row lines connected to control gates of the floating gate electric field effect transistors arranged in a row direction,
• a plurality of column lines connected to drains of the floating gate electric field effect transistors arranged in a column direction, and
• a common line commonly connected to sources of the floating gate electric field effect transistors constituting a block;
• and
• a erase processing means which performs erase processing where, by controlling voltages applied to the row lines, the column lines and the common wiring,
• firstly write before erase is performed,
• secondly write-verify before erase is performed,
• thirdly an erase pulse is applied,
• fourthly verify after erase pulse application is performed,
• fifthly first verify is performed to detect an overerased cell,
• sixthly, when an overerased cell is detected in the first verify by applying a voltage to one of the row lines, second verify is performed to specify the overerased cell by applying a voltage different from the voltage applied in the first verify to the row line, and
• seventhly, when the overerased cell is specified as a result of the second verify, write of a software program is performed for the overerased cell.