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US 2003/0067346 A1Published application
Reference voltage circuit
AssigneeInfineon Technologies AG
InventorRichard Gaggl
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AssigneeInfineon Technologies AG
InventorRichard Gaggl
Estimating the term…
Reference voltage circuit for generating at least one constant reference voltage (Vref) with a first current mirror circuit (54), which is connected to a positive supply voltage (Vdd) and mirrors a reference current (Iref) with a first current mirror factor (N1) to form a first mirrored reference current (IS1); a second current mirror circuit (67), which is connected to a negative supply voltage (Vss) and mirrors a reference current (Iref) with a second current mirror factor (N2) to form a second mirrored reference current (IS2); a resistor string (71), which comprises a plurality of resistors (71-i) connected in series and is wired between the two current mirror circuits (54, 67); one end (42) of the resistor string (71) being supplied with the first mirrored reference current (IS1) from the first current mirror circuit (54) and the other end (73) of the resistor string (71) delivering the second mirrored reference current (IS2) to the second current mirror circuit (67), the two current mirror factors (N1, N2) of the current mirror circuits (54, 67) being equal, so that constant reference voltages can be picked off at the resistors (71-i) of the resistor string (71).
A reference voltage circuit for generating at least one constant reference voltage (Vref) with:
The reference voltage circuit as claimed in one of the preceding claims, wherein the reference voltages are picked off at high impedance at the resistor string (71).
The reference voltage circuit as claimed in one of the preceding claims, wherein there is an even number of resistors within the resistor string (71).
The reference voltage circuit as claimed in one of the preceding claims, wherein no current flows away at the center tap (74) of the resistor string 71.
The reference voltage circuit as claimed in one of the preceding claims, wherein the reference current (Iref) is generated by a voltage-controlled current source (44).
The reference voltage circuit as claimed in one of the preceding claims, wherein the reference voltage circuit (2) is integrated in a semiconductor chip (1).
The reference voltage circuit as claimed in one of the preceding claims, wherein the center tap (74) of the resistor string (71) is connected to a reference-voltage terminal pad (37) of the semiconductor chip (1).
The reference voltage circuit as claimed in one of the preceding claims, wherein the generated reference voltages (Vref) lie symmetrically between the positive supply voltage (Vdd) and the negative supply voltage (Vss).
Dependencies are inferred from the claim text.