Variable threshold voltage double gated transistors and method of fabrication

A method for forming a plurality of field effect transistors having different threshold voltages, the method comprising the steps of:

• a) providing a silicon-on-insulator substrate, the silicon-on-insulator substrate comprising a silicon layer on a buried dielectric layer;
• b) forming a mandrel layer on the silicon layer;
• patterning the mandrel layer to define a plurality of mandrel layer edges;
• c) patterning the silicon layer with the plurality of mandrel layer edges, the patterning of the silicon layer providing a plurality of first body edges;
• d) forming a plurality of first gate dielectrics on the plurality of first body edges;
• e) providing a plurality of first gate structures of a first work-function adjacent the first body edges on the plurality of first gate dielectrics;
• f) patterning the mandrel layer to expose a first edges of the plurality of first gate structures;
• g) forming a plurality of sidewall spacers adjacent the first edges of the plurality of first gate structures, the sidewall spacers having a sidewall spacer width;
• h) adjusting the width of selected sidewall spacers;
• i) patterning the silicon layer with plurality of sidewall spacers, the pattering of the silicon layer providing a plurality of second body edges, where the first and second body edges of the patterned silicon layer define a plurality of transistor bodies;
• j) providing a plurality of second gate dielectrics on the plurality of second body edges;
• and
• k) providing a plurality of second gate structures of a second work-function adjacent the second body edges on the plurality of second gate dielectrics.

A plurality of transistors comprising:

• a) a plurality of transistor bodies formed on a substrate, the transistor bodies each having a first vertical edge and a second vertical edge defining a transistor body width, wherein a selected portion of the plurality of transistor bodies has an adjusted width;
• b) a plurality of first gate structures, each of the plurality of first gate structures adjacent to one of the plurality of transistor body first vertical edges, the plurality of first gate structures having a first work-function;
• and
• c) a plurality of second gate structures, each of the plurality of second gate structures adjacent to one of the plurality of transistor body second vertical edges, the plurality of second gate structures having a second work-function.