Interconnect circuitry, multichip module, and methods of manufacturing thereof

A multichip module comprising:

• a plurality of integrated circuits mounted on a substrate;
• one or more dielectric layers comprised of a flexible dielectric material;
• and
• one or more layers of electrically conductive material patterned to form multiple electrical interconnects between bonding pads on different ones of said integrated circuits, with each such layer placed on top of one of said dielectric layers.

A method of manufacturing a multichip module comprising:

• placing a frame on a first flat substrate, said frame having holes in it for positioning and holding integrated circuit chips;
• placing integrated circuit chips through frame to planarize their top, active, surfaces against the first flat substrate;
• removing the first substrate from the frames and the chips;
• placing one or more layers of dielectric on top of the frames and chips;
• using photolithographic techniques to etch vias through each of the one or more dielectric layers to allow selective contact to conductive bonding pads on individual chips or conductive paths on a dielectric layer below;
• using photolithographic techniques to lay down conductive material in such vias and in desired conductive pathways on the currently to layer of dielectric material.

A method of manufacturing a multichip module comprising:

• placing integrated circuit chips against a first flat substrate to planarize their top, active, surfaces against said first substrate;
• placing epoxy on the back of said chips;
• attaching the chips to a second substrate on the opposite side of the chips from the first substrate;
• removing the first substrate;
• filling space between chips with fluid filler material that can be hardened into a relatively flexible material;
• hardening said filler material;
• placing one or more additional layers of dielectric material on top of the filler material and the chips;
• using photolithographic techniques to etch vias through each of said additional dielectric layer to allow selective contact to conductive bonding pads on chips or conductive paths on dielectric layer below;
• and
• using photolithographic techniques to lay down conductive material in vias and in desired conductive pathways on the current top dielectric layer.