Method and apparatus for scalable error correction code generation performance
AssigneeAdaptec, Inc.
InventorDonald N. Allingham
Life of this patent
Estimating the term…
Loading patent…
AssigneeAdaptec, Inc.
InventorDonald N. Allingham
Estimating the term…
A scalable memory controller for use in connection with error correction code is provided. According to the invention, the channels of the controller are interconnected to a plurality of parity engines and associated cache memories using a switched fabric architecture. A processor is provided for allocating operations requiring access to the parity engines or cache memories. By providing multiple parity engines and cache memories, error correction syndrome values can be calculated in parallel. The performance of the controller can be selectively scaled by providing a greater or lessor number of parity engines and associated cache memories. Furthermore, by utilizing a switched fabric internal architecture, data transfers between the internal components of the controller can be conducted simultaneously.
A scalable method for reducing latency associated with computer data parity calculations, comprising:
A method for providing parity calculations in connection with computer memory, comprising:
A RAID controller, comprising:
The RAID controller of claim 20, further comprising a second interface, wherein said switch is capable of selectively interconnecting said second interface to a one of said plurality of parity engines.
The RAID controller of claim 20, further comprising a processor, wherein said processor provides said first interface with a first address for said first block of data, wherein said switch directs said first block of data to a one of said plurality of parity engines having said first address, and wherein said processor provides said first interface with a second address for said second block of data, and wherein said switch directs said second block of data to a one of said plurality of parity engines having said second address.
Dependencies are inferred from the claim text.