Method of using sacrificial spacers to reduce short channel effect

A method of forming a semiconductor device, comprising the sequential steps of:

• providing a silicon substrate having a gate electrode stack formed thereover;
• the silicon substrate having an exposed surface;
• the gate electrode stack including a lower portion with exposed side walls;
• forming a first thermal oxide layer over:
• the exposed side walls of the lower portion of the gate electrode stack;
• and
• the exposed surface of the silicon substrate;
• using the gate electrode stack and the first thermal oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack as masks, implanting LDD implants into the silicon substrate adjacent the first thermal layer over the exposed sidewalls of the lower portion of the gate electrode stack;
• forming a conformal SiN layer over the gate electrode stack and the first thermal oxide layer;
• forming a sacrificial oxide layer over the conformal SiN layer;
• patterning the horizontal portions of the sacrificial oxide layer, the conformal SiN layer and the underlying portions of the first thermal oxide layer to form:
• sacrificial oxide spacers;
• L-shaped conformal SiN spacers thereunder;
• and
• L-shaped first thermal oxide layer spacers thereunder;
• using the gate electrode stack and the sacrificial oxide spacers as masks, implanting source/drain implants adjacent the sacrificial oxide spacers;
• and
• removing the sacrificial oxide spacers.

A method of forming a semiconductor device, comprising the sequential steps of:

• providing a substrate having a gate electrode stack formed thereover;
• the substrate having an exposed surface;
• the gate electrode stack including a lower portion with exposed side walls;
• forming a first oxide layer over:
• the exposed side walls of the lower portion of the gate electrode stack;
• and
• the exposed surface of the substrate;
• using the gate electrode stack and the first oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack as masks, implanting LDD implants into the substrate adjacent the first oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack;
• forming a conformal dielectric layer over the gate electrode stack and the first oxide layer;
• patterning the conformal dielectric layer and the underlying portions of the first oxide layer to form:
• conformal dielectric spacers;
• and
• L-shaped first oxide layer spacers thereunder;
• forming sacrificial dielectric spacers over the conformal dielectric spacers;
• using the gate electrode stack, the conformal dielectric spacers and the sacrificial dielectric spacers as masks, implanting source/drain implants adjacent the sacrificial dielectric spacers;
• and
• removing the sacrificial dielectric spacers.

A method of forming a semiconductor device, comprising the sequential steps of:

• providing a silicon substrate having a gate electrode stack formed thereover;
• the silicon substrate having an exposed surface;
• the gate electrode stack including a lower portion with exposed side walls;
• forming a thermal oxide layer over:
• the exposed side walls of the lower portion of the gate electrode stack;
• and
• the exposed surface of the silicon substrate;
• using the gate electrode stack and the thermal oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack as masks, implanting LDD implants into the silicon substrate adjacent the thermal oxide layer over the exposed sidewalls of the lower portion of the gate electrode stack;
• forming a conformal dielectric layer over the gate electrode stack and the thermal oxide layer;
• the conformal dielectric layer being comprised of nitride or silicon nitride;
• patterning the conformal dielectric layer and the underlying portions of the thermal oxide layer to form:
• conformal dielectric spacers;
• and
• L-shaped thermal oxide layer spacers thereunder;
• forming sacrificial dielectric spacers over the conformal dielectric spacers;
• the sacrificial dielectric spacers being comprised CVD oxide or CVD silicon oxide
• using the gate electrode stack, the conformal dielectric spacers and the sacrificial dielectric spacers as masks, implanting source/drain implants adjacent the sacrificial dielectric spacers;
• and
• removing the sacrificial dielectric spacers.