Self aligned gate

A method for making a polysilicon gate in an integrated circuit, the method comprising the steps of:

• forming a silicon oxide gate layer on a semiconducting substrate,
• forming a polysilicon gate layer on the gate layer,
• oxidizing the gate layer to form a silicon oxide blocking layer on the gate layer,
• masking the blocking layer with a photoresist layer,
• developing the photoresist layer to define an exposed gate area,
• etching the blocking layer in the gate area to expose the gate layer in the gate area,
• removing the photoresist layer,
• forming a metal layer on the blocking layer and on the gate layer in the gate area,
• selectively reacting the metal layer with the gate layer in the gate area to form a silicide hard mask over the gate layer in the gate area,
• removing the metal layer from the blocking layer,
• selectively etching the blocking layer without substantially etching the hard mask in the gate area, to expose the gate layer surrounding the gate area, and
• etching the exposed gate layer to define a gate in the gate area,
• where the hard mask remains on the gate and functions as an electrical contact to the gate.

A method for making a polysilicon gate in an integrated circuit, the method comprising the steps of:

• forming a silicon oxide gate layer on a semiconducting substrate,
• forming a polysilicon gate layer on the gate layer,
• oxidizing the gate layer to form a silicon oxide blocking layer on the gate layer,
• forming an anti-reflective layer on the blocking layer,
• masking the anti-reflective layer with a negative photoresist layer and exposing the negative photoresist layer using a positive photoresist mask, where the positive photoresist mask is typically used to expose a positive photoresist layer prior to a gate etch process,
• developing the photoresist layer to define an exposed gate area,
• etching the anti-reflective layer and the blocking layer in the gate area to expose the gate layer in the gate area,
• removing the photoresist layer,
• removing the anti-reflective layer,
• forming a metal layer on the blocking layer and on the gate layer in the gate area,
• selectively reacting the metal layer with the gate layer in the gate area to form a silicide hard mask over the gate layer in the gate area,
• removing the metal layer from the blocking layer,
• selectively etching the blocking layer without substantially etching the hard mask in the gate area, to expose the gate layer surrounding the gate area,
• etching the exposed gate layer to define a gate in the gate area, where the hard mask remains on the gate and functions as an electrical contact to the gate, and
• defining source drain areas adjacent the gate using ion implantation to self align the gate with the integrated circuit.