Common source EEPROM and flash memory
AssigneeVirtual Silicon Technology, Inc.
InventorsAlbert Bergemont, Gregorio Spadea
Life of this patent
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Abstract
A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.
Claims9
An array of nonvolatile memory cells arranged in a plurality of rows and columns comprising:
- a wordline associated with each row of the array;
- a bitline associated with each column of the array;
- a plurality of nonvolatile memory transistors, each of said nonvolatile memory transistors associated with one row and one column in the array, each nonvolatile memory transistor having a source, a drain, a floating gate and a control gate, the control gate of each nonvolatile memory transistor coupled to the one of said wordlines with which its row is associated, the drain of each nonvolatile memory transistor coupled to the one of said bitlines with which its column is associated;
- the source of each nonvolatile memory transistor in a row of the array coupled together;
- and
- a source transistor associated with each row of the array each said source transistor having a gate coupled to the one of said wordlines with which its row is associated, a source coupled to a source potential line, and a drain coupled to the sources of each nonvolatile memory transistor with which its row is associated.
The array of claim 3, further comprising a well selection transistor coupled to said isolation well.
An array of nonvolatile memory cells arranged in a plurality of rows and columns further comprising:
- a wordline associated with each row of the array;
- a bitline associated with each column of the array;
- a plurality of split-gate nonvolatile memory transistors, each of said split-gate nonvolatile memory transistors associated with one row and one column in the array, each split-gate nonvolatile memory transistor having a source, a drain, a floating gate and a control gate, the control gate of each split-gate nonvolatile memory transistor coupled to the one of said wordlines with which its row is associated, the drain of each split-gate nonvolatile memory transistor coupled to the one of said bitlines with which its column is associated;
- the source of each split-gate nonvolatile memory transistor in adjacent pairs of rows of the array coupled together;
- and
- a source transistor associated with each row of the array each said source transistor having a gate coupled to the one of said wordlines with which its row is associated, a source coupled to a source potential line, and a drain coupled to the sources of each nonvolatile memory transistor with which its row is associated.
An array of one-time programmable nonvolatile memory cells arranged in a plurality of rows and columns comprising:
- a wordline associated with each row of the array;
- a bitline associated with each column of the array;
- a plurality of nonvolatile memory transistors, each of said nonvolatile memory transistors associated with one row and one column in the array, each nonvolatile memory transistor having a source, a drain, and a floating gate, the source of each nonvolatile memory transistor coupled to the one of said wordlines with which its row is associated, the drain of each nonvolatile memory transistor coupled to the one of said bitlines with which its column is associated;
- and
- a source transistor associated with each row of the array each said source transistor having a gate coupled to the one of said wordlines with which its row is associated, a source coupled to a source potential line, and a drain coupled to the sources of each nonvolatile memory transistor with which its row is associated.
Dependencies are inferred from the claim text.