Alternating reference wordline scheme for fast dram

A method of controlling a fast dynamic random access memory (DRAM) with ground-sensing, comprising the steps of:

• in a first cycle:
• restoring a bitline pair to around potential;
• connecting a first DRAM cell to a first bitline in said bitline pair causing said DRAM cell to share a charge stored therein with said first bitline;
• connecting a first in a pair of reference cells to a second bitline causing said first reference cell to share a reference charge stored therein with said second bitline;
• and
• sensing a voltage difference between said first and second bitlines;
• in subsequent cycles:
• restoring said bitline pair to ground potential;
• connecting another DRAM cell to said first bitline causing said another DRAM cell to share a charge stored therein with said first bitline;
• alternately connecting said first and a second of said reference cell pair to said second bitline causing said connected reference cell share a reference charge stored therein with said second bitline;
• and
• sensing a voltage difference between said first and second bitlines.

A method of operating a fast dynamic random access memory (DRAM), comprising the steps of:

• providing a first pair of reference cells to a bitline true (BLT);
• providing a second pair of reference cells to a bit line complement (BLC);
• and
• alternately connecting first and second reference cells in said first pair of reference cells to said BLT when a memory cell is connected to said BLC on successive cycles, and alternately connecting first and second reference cells in said second pair of reference cells to said BLC when a memory cell is connected to said BLT on successive cycles.