Conductor chemical-mechanical polishing in integrated circuit interconnects
OwnerKashmir S. Sahota, Kai Yang +1inventors
InventorsKashmir S. Sahota, Kai Yang, Steven C. Avanzino
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Abstract
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a fixed abrasive polish pad, a very thin barrier layer may be used without the conductor core and the dielectric layer being subject to erosion or dishing.
Claims15
An integrated circuit comprising:
- a semiconductor substrate having a semiconductor device provided thereon;
- a dielectric layer formed on the semiconductor substrate having an opening provided therein;
- a barrier layer lining the opening and having a thickness of less than 8% of the depth of the opening;
- and
- a conductor core filling the opening and connected to the semiconductor device, the conductor core and barrier layer having a combined thickness equal to the thickness of the dielectric layer.
An integrated circuit comprising:
- a silicon substrate having a semiconductor device provided thereon;
- a device oxide layer deposited on the silicon substrate;
- a channel oxide layer formed on the device oxide layer having a channel opening provided therein;
- a barrier layer lining the channel opening and having a thickness of less than 8% of the depth of the opening;
- and
- a conductor core filling the channel opening and connected to the semiconductor device, the conductor core over the barrier layer, the conductor core and barrier layer having a combined thickness equal to the thickness of the channel oxide layer.
A method of manufacturing an integrated circuit comprising:
- providing a semiconductor substrate having a semiconductor device provided thereon;
- forming a dielectric layer on the semiconductor substrate;
- forming a opening in the dielectric layer;
- depositing a barrier layer to line the opening;
- depositing a conductor core over the barrier layer to fill the opening and connect to the semiconductor device;
- and
- chemical-mechanical polishing the conductor core using a solution having at least a 200:1 selectivity from the conductor core to the barrier layer.
A method of manufacturing an integrated circuit comprising:
- providing a semiconductor substrate having a semiconductor device provided thereon;
- depositing a device oxide layer on the semiconductor substrate;
- depositing a channel oxide layer on the device oxide layer;
- forming a channel opening in the channel oxide layer;
- depositing a barrier layer to line the channel opening;
- depositing a conductor core to fill the channel opening and connect to the semiconductor device;
Dependencies are inferred from the claim text.