Method for preventing gate depletion effects of MOS transistor
AssigneeMacronix International Co., Ltd.
InventorKent Kuohua Chang
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Abstract
The present invention shows a method of fabricating a MOS transistor on the substrate of a semiconductor wafer and of preventing the gate depletion effects occurring in the MOS transistor. The method involves first forming a silicon oxide layer on the substrate. Then an amorphous silicon layer is formed on the silicon oxide layer followed by forming a silicon germanium (Si1-xGex, x=0.05˜1.0) layer on the amorphous silicon layer. Thereafter, an etching process removes portions of the silicon germanium layer and the amorphous silicon layer so as to form gates of the MOS transistor on the substrate. Finally, a spacer is formed around each gate and a source and a drain of each MOS transistor is formed in the substrate.
Claims19
A method of forming a metal-oxide semiconductor (MOS) transistor on a substrate of a semiconductor wafer and of preventing gate depletion effects occurring in the MOS transistor, the method comprising:
- forming a silicon oxide layer on the substrate;
- forming an amorphous silicon layer on the silicon oxide layer;
- forming a silicon germanium layer on the amorphous silicon layer;
- performing an etching process to etch the silicon germanium layer and the amorphous silicon layer so as to form a gate of the MOS transistor on the substrate;
- forming a spacer around the gate;
- and
- forming a source and a drain of the MOS transistor in the substrate.
A MOS transistor fabricating method of preventing gate depletion effects occurring in the MOS transistor, the method comprising:
- providing a semiconductor wafer;
- forming a silicon oxide layer on the silicon substrate of the semiconductor wafer;
- forming an amorphous silicon layer on the silicon oxide layer;
- performing an in-situ doped chemical vapor deposition (CVD) process for forming a silicon germanium layer on the amorphous silicon layer;
- performing an etching process to etch the silicon germanium layer and the amorphous silicon layer so as to form a gate of the transistor on the substrate;
- forming a spacer around the gate;
- performing a first ion implantation process to form two doped areas on two sides of the gate on the silicon substrate;
- and
- performing a high temperature annealing process to drive in the dopants in the two doped areas for forming a source and a drain of the MOS transistor;
- wherein the high temperature annealing process diffuses germanium atoms in the silicon germanium layer into the amorphous silicon layer so as to transform the amorphous silicon layer to silicon germanium, furthermore, to suppress gate depletion effects occurring in the MOS transistor.
Dependencies are inferred from the claim text.