Method for fabricating a mos transistor of an embedded memory

A method for fabricating a metal oxide semiconductor (MOS)

• transistor of an embedded memory, the method comprising:
• providing a semiconductor wafer with both a memory array area and a periphery circuit region defined on the surface of the silicon substrate of the semiconductor wafer, the memory array area comprising at least one cell-well, the periphery circuit region comprising at least one N-well and at least one P-well;
• forming a first dielectric layer, a doped polysilicon layer, a passivation layer, and a first photoresist layer in sequence on the surface of the semiconductor wafer;
• performing a first photolithographic process so as to define a plurality of gate patterns in the first photoresist layer above the cell-well of the memory array area;
• using the gate patterns in the first photoresist layer as a hard mask to etch the passivation layer and the doped polysilicon layer located both in the memory array area and in the periphery circuit region down to the surface of the first dielectric layer so as to form each gate in the memory array area;
• removing the first photoresist layer;
• forming a first spacer on sidewalls of each gate in the memory array area;
• performing a first ion implantation process to form a lightly doped drain (LDD) adjacent to each gate in the memory array area;
• forming a stop layer and a second dielectric layer in sequence on the surface of the semiconductor wafer;
• performing an etch-back process to remove the second dielectric layer located in the periphery circuit region;
• removing the stop layer located in the periphery circuit region;
• forming an undoped polysilicon layer and a second photoresist layer in sequence on the surface of the semiconductor wafer;
• performing a second photolithographic process to define a plurality of gate patterns in the second photoresist layer above the N-well and P-well of the periphery circuit region;
• using the gate patterns of the second photoresist layer as a hard mask to etch the undoped polysilicon layer down to the surface of the first dielectric layer so as to form the gates in the periphery circuit region;
• removing the second photoresist layer;
• performing a second ion implantation process to form a lightly doped drain (LDD) adjacent to each gate in the periphery circuit region;
• forming a silicon nitride layer on the surface of the semiconductor wafer covering each gate in located in the periphery circuit region;
• etching the silicon nitride layer adjacent to each gate on the P-well of the periphery circuit region to form a plurality of second spacers, and performing a third ion implantation process to form a source and a drain of each NMOS transistor within the P-well;
• etching the silicon nitride layer adjacent to each gate on the N-well of the periphery circuit region to form a plurality of third spacers, and performing a fourth ion implantation process to form a source and a drain of each PMOS transistor within the N-well;
• and
• performing a self-aligned silicide (salicide) process to respectively form a metal silicide layer on the top surface of each gate, and on the surface of each source and drain in the periphery circuit region.