Method for manufacturing components on an SOI wafer
AssigneeATMEL Germany GmbH
InventorsHarry Dietrich, Volker Dudek, Andreas Schueppen
Life of this patent
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Abstract
Method for manufacturing components on an SOI wafer. In the previously known methods, the differing electrical requirements of the MOS and bipolar transistors in respect of the thickness of the silicon layer lying on the insulating intermediate layer hinder the integration of the different types of components on one wafer. According to the new method, the requirements regarding the thickness, in particular those for the bipolar transistors, are substantially reduced by implanting buried silicided areas because the previous “buried-layer” is replaced by a thin, low ohmic silicide layer. Furthermore, the HF characteristics of the MOS-transistors can be improved by the buried silicide areas.
Claims40
Method for manufacturing components on a silicon wafer (100) from a first silicon wafer (110), consisting of a surface layer on an insulating intermediate layer (901) arranged on a substrate (900), and a second silicon wafer (400) with a surface by bonding the two wafers (110, 400) by their respective surfaces by means of a so-called wafer-bonding, wherein
- at least one silicided area (414, 415, 416) is created on the first silicon wafer (100) within or upon the surface of the surface layer before bonding, and
- at least one insulating layer is subsequently applied to the surface of at least one silicon wafer (110,400), and
- the substrate (900) and at least part of the insulating layer (901) of the first silicon wafer (110) is removed after bonding, and
- at least one component is subsequently manufactured in the surface layer of the silicon wafer (100) in a series of a plurality of process steps.
Dependencies are inferred from the claim text.