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US 2002/0171452 A1Published application
Circuits, architectures, and methods for generating a periodic signal in a memory
AssigneeCypress Semiconductor Corporation
InventorsJOHNIE AU, PIDUGU L. NARAYANA, SANGEETA THAKUR
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Abstract
A circuit comprising a clock generator and a state machine. The clock generator may be configured to generate an output clock signal in response to (i) a first enable signal and (ii) a second enable signal. The state machine may be configured to generate the second enable signal in response to a first and a second control signal.
Claims18
A circuit comprising:
- a clock generator circuit configured to generate an output clock signal in response to (i) a first enable signal and (ii) a second enable signal;
- and
- a state machine configured to generate said second enable signal in response to a first and a second control signal.
A circuit comprising:
- means for generating an output clock signal in response to (i) a first enable signal and (ii) a second enable signal;
- and
- means for generating said second enable signal in response to a first and a second control signal.
A method for generating an output clock signal comprising the steps of:
- (A) generating said output clock signal in response to (i) a first enable signal and (ii) a second enable signal;
- and
- (B) generate said second enable signal in response to a first and a second control signal.
Dependencies are inferred from the claim text.