US 2002/0164847 A1Published application

Method of forming a CMOS type semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsDo-Hyung Kim, Jin-Ho Kim, Byung-Jun Hwang

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Abstract

A method of forming a CMOS type semiconductor device comprises forming a gate electrode pattern on a surface of a substrate in NMOS and PMOS regions, forming spacers on side walls of the gate electrode pattern in the NMOS and PMOS regions, and doping n and p-type impurities heavily to the surface of the substrate in the NMOS and PMOS regions, respectively. After doping the p and n-type impurities heavily, the spacers are removed. The method further includes doping the n and p-type impurities lightly to the surface of the substrate in the NMOS and PMOS regions on which the spacers are removed. Alternatively, the light impurity implantation can be carried out before forming the spacers. Also, the light impurity implantation can be carried out to the surface of the substrate in one of the NMOS and PMOS regions before forming the spacers and to the surface of the substrate in the other of the NMOS and PMOS regions after removing the spacers.

Claims8

Dependent claims

A method of forming a CMOS type semiconductor device comprising the steps of:

forming a gate electrode pattern on a surface of a substrate in NMOS and PMOS regions;
forming spacers on side walls of said gate electrode pattern in said NMOS and PMOS regions;
forming a first photo-resist pattern exposing one of said NMOS and PMOS regions;
heavily doping a first conductive impurity using said first photo-resist pattern as an impurity implantation mask;
removing said first photo-resist pattern;
forming a second photo-resist pattern exposing the other of said NMOS and PMOS regions;
heavily doping a second conductive impurity to the other of said NMOS and PMOS regions;
removing said spacers formed on said side walls of said gate electrode pattern in the other of said NMOS and PMOS regions using said second photo-resist pattern as an etch mask;
lightly doping said second conductive impurity to the other of said NMOS and PMOS regions;
removing said second photo-resist pattern;
and
removing said spacers formed on said side walls of said gate electrode pattern in said one of said NMOS and PMOS regions.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/017,237Filed 14 Dec 2001
Priority: KR 2001-243314 May 2001
Published: 7 Nov 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0184
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate sidewall spacers
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D
Inorganic electric semiconductor devices