Method and apparatus for reducing color conflicts during trim generation for phase shifters

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for generating trim to be used in conjunction with phase shifters during an optical lithography process for manufacturing an integrated circuit, the method comprising:

• identifying a feature within the integrated circuit to be created by using a phase shifter to produce a region of destructive light interference on a photoresist layer;
• generating the phase shifter within a first mask;
• wherein generating the phase shifter involves ensuring that design rules are satisfied in defining dimensions for the phase shifter;
• and
• after the phase shifter is generated, generating trim within a second mask to be used in conjunction with the first mask;
• wherein generating the trim involves deriving the trim from the previously-defined dimensions of the phase shifter while ensuring that the design rules are satisfied.

A set of masks for generating trim to be used in conjunction with phase shifters during an optical lithography process for manufacturing an integrated circuit, comprising:

• a first mask;
• a phase shifter within the first mask that produces a region of destructive light interference on a photoresist layer;
• wherein dimensions of the phase shifter satisfy design rules;
• a second mask;
• and
• trim within the second mask to be used in conjunction with the first mask;
• wherein the trim is derived from the previously-defined dimensions of the phase shifter while ensuring that the design rules are satisfied.

An integrated circuit produced using an optical lithography process, comprising:

• a feature within the integrated circuit created by using a phase shifter located on a first mask to produce a region of destructive light interference on a photoresist layer;
• wherein dimensions of the phase shifter satisfy design rules;
• wherein the feature is additionally created by using trim within a second mask in conjunction with the phase shifter in the first mask;
• wherein the trim is derived from previously-defined dimensions of the phase shifter while ensuring that design rules are satisfied.

A means for generating trim to be used in conjunction with phase shifters during an optical lithography process for manufacturing an integrated circuit, comprising:

• an identification means for identifying a feature within the integrated circuit to be created by using a phase shifter to produce a region of destructive light interference on a photoresist layer;
• a phase shifter generating means for generating the phase shifter within a first mask;
• wherein generating the phase shifter involves ensuring that design rules are satisfied in defining dimensions for the phase shifter;
• and
• a trim generation means for generating trim within a second mask to be used in conjunction with the first mask;
• wherein generating the trim involves deriving the trim from the previously-defined dimensions of the phase shifter while ensuring that design rules are satisfied.

A set of masks for generating trim to be used in conjunction with phase shifters during an optical lithography process for manufacturing an integrated circuit, comprising:

• a first mask;
• a phase shifter within the first mask that produces a region of destructive light interference on a photoresist layer;
• wherein the phase shifter in the first mask is used to expose a first polysilicon line in a gate region of a first transistor in the integrated circuit;
• wherein dimensions of the phase shifter satisfy design rules;
• a second mask;
• trim within the second mask to be used in conjunction with the first mask;
• wherein the trim in the second mask is used to protect the first polysilicon line from exposure during use of the second mask;
• wherein the trim is derived from the previously-defined dimensions of the phase shifter while ensuring that the design rules are satisfied;
• and
• a second polysilicon feature defined within the second mask and in close proximity to a portion of the trim located on one side of the first polysilicon line, such that if the portion of the trim were of a default size a design rule violation would occur between the portion of the trim and the second polysilicon feature;
• wherein the portion of the trim is derived to be less that the default size so that the design rule violation.