Dram cell configuration and method for fabricating the dram cell configuration
AssigneeInfineon Technologies AG
InventorsHerbert Benzinger, Frank Richter
Life of this patent
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Abstract
A DRAM cell configuration is described in which a memory cell in each case has a storage capacitor and a read-out transistor. For connecting to the read-out transistor, a buried strap contact is produced by outdiffusion of dopants from the electrode of the storage capacitor. The buried strap contact is superposed by the implantations of the source/drain region of the read-out transistor, so that the implantations of the source/drain region form the boundary of the space charge zone of a p/n junction of the memory cell.
Claims16
A dynamic random access memory (DRAM) cell configuration, comprising:
- a semiconductor substrate having trenches formed therein;
- an insulating layer having an opening formed therein;
- storage capacitors disposed in said trenches of said semiconductor substrate, each of said storage capacitors having an electrode being isolated from said semiconductor substrate by said insulating layer;
- read-out transistors, each of said read-out transistors assigned to an associated one of said storage capacitors, each of said read-out transistors having a gate electrode and a source/drain region produced by implantation of dopants and disposed in said semiconductor substrate, said source/drain region connected to said electrode of an associated one of said storage capacitors through said opening in said insulating layer;
- and
- buried strap contacts, each of said buried strap contacts associated with a respective storage capacitor and connected to said source/drain region of a respective read-out transistor by outdiffusion of further dopants from said electrode of said respective storage capacitor and a type of doping of said outdiffusion and of said implantation being identical, said implantation of said source/drain region in each case extending at least as deeply into said semiconductor substrate as said outdiffusion of said buried strap contacts so that said implantation of said source/drain region forms a boundary of a space charge zone of a p/n junction.
A method for fabricating a dynamic random access memory (DRAM) cell configuration, which comprises the steps of:
- providing a semiconductor substrate;
- fabricating trenches in the semiconductor substrate;
- fabricating insulator layers with openings and electrodes of storage capacitors in the trenches;
- outdiffusing of dopants from the electrodes through the openings for producing buried strap contacts for connection to read-out transistors associated with the storage capacitors;
- forming gate electrodes of the read-out transistors on the semiconductor substrate;
- and
- producing source/drain regions of the read-out transistors by selective implantation of further dopants into interspaces between the storage capacitors and the gate electrodes at least as deeply into the semiconductor substrate as outdiffusions formed by the buried strap contacts, a type of doping of the outdiffusions of the buried strap contacts and of the implantations being identical.
Dependencies are inferred from the claim text.