Multi-layer substrate for an IC chip
OwnerChung-Ju Wu, Chia-Wen Shih +2inventors
InventorsChung-Ju Wu, Chia-Wen Shih, Chen-Wen Tsai, Wei-Feng Lin
Life of this patent
Estimating the term…
Abstract
A multi-layer substrate for an IC chip having a plurality of pads comprises a first layer having a plurality of conducting lines electrically connected to the pads of the IC chip, whereby a first current is generated in the conducting lines, and a second layer has a ground plane electrically connected to a ground, and a plurality of via holes penetrating the second layer and the conducting plane, wherein the via holes are arranged to make a second current in the conducting plane induced by the first current flowing to the ground.
Claims16
A multi-layer substrate for an IC chip having a plurality of pads comprising:
- a first layer having a plurality of conducting lines electrically connected to the pads of the IC chip, whereby a first current is generated in the conducting lines;
- and
- a second layer having a ground plane electrically connected to a ground, and a plurality of via holes penetrating the second layer and the conducting plane, wherein the via holes are arranged to create a second current in the conducting plane induced by the first current flowing to the ground.
A method for arranging via holes of a multi-layer substrate for an IC chip having a plurality of pads, the method comprising the steps of:
- providing a first layer having a plurality of conducting lines electrically connected to the pads of the IC chip, and a second layer having a ground plane electrically connected to a ground and a plurality of via holes penetrating the second layer and the conducting plane;
- generating a first current in the conducting lines, which induces a second current in the ground plane;
- and
- arranging the via holes to make the second current flowing to the ground.
Dependencies are inferred from the claim text.