Method and apparatus for reducing isolation stress in integrated circuits

A method for forming an oxidation mask on a silicon substrate, comprising:

• forming a layer of silicon nitride on a base layer;
• and
• continuously varying the silicon content in the silicon nitride layer as it is formed to reduce stress of the silicon nitride layer wherein the silicon content of the silicon nitride layer is graded substantially linearly.

A method for forming an oxidation mask on a silicon substrate, comprising:

• forming a layer of silicon nitride on a base layer;
• and
• continuously varying the silicon content in the silicon nitride layer as it is formed to reduce stress of the substrate caused by the silicon nitride layer wherein the silicon content of the silicon nitride layer is graded substantially non-linearly.

A method for forming an oxidation mask on a silicon substrate, comprising:

• forming a pad layer of oxide-nitride-oxide on the base layer forming a layer of silicon nitride on the pad layer;
• and
• varying the silicon content in the silicon nitride layer as it is formed to reduce stress of the the silicon nitride layer wherein the silicon content of the silicon nitride layer is graded substantially linearly.

A method for forming an oxidation mask on a substrate, comprising:

• forming a base layer on at least a portion of the surface of the substrate;
• and
• forming a layer of silicon nitride on the base layer which has a silicon concentration that varies from a first silicon concentration adjacent the base layer to a second silicon concentration at the top surface of the layer of silicon nitride with the first and second silicon concentrations selected for generating opposing mechanical stresses to the bottom portion of the layer relative to the top portion of the layer.

An isolation structure supported by a substrate, comprising:

• a varied silicon content silicon nitride layer having a sidewall profile angle that reduce stress of the silicon nitride layer.