US 2002/0163027 A1 · Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and an integrated circuit including this kind of transistor

Abstract

The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.

Claims28

Dependent claims

A method of fabricating a vertical insulated gate transistor, the method comprising:

forming a vertical semiconductor pillar with one or more flanks on a semiconductor substrate;
and
forming a dielectrically isolated semiconductor gate with a cavity, so that the gate is resting on the flanks of the pillar and on the substrate;
wherein the step of forming the vertical semiconductor pillar includes forming a primary semiconductor pillar resting on the substrate and forming the cavity in the primary pillar;
and
wherein the step of forming the gate further includes coating one or more internal walls of the cavity with an isolating layer and filling the cavity with a gate material so as to form between a portion of the gate situated in the cavity and a portion of the gate resting on the flanks of the pillar two connecting semiconductor regions extending between a source region and a drain region of the transistor.

3 more elements

Dependencies are inferred from the claim text.

Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and an integrated circuit including this kind of transistor

Life of this patent

Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and an integrated circuit including this kind of transistor

Life of this patent

Abstract

Claims28