Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process

A lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process, comprising:

• a P type silicon substrate;
• a plurality of shallow trench isolations formed in said substrate;
• a N well and a P well adjacent thereto formed between one pair of said shallow trench isolations in said substrate;
• a dummy gate formed on said N well;
• a N type polysilicon gate formed on said P well and connected to a cathode terminal;
• two first N+ diffusion region respectively formed beside each side of said N type polysilicon gate, one said first N+ diffusion region between said N type polysilicon gate and said dummy gate and across one portion of said N well and one portion of said P well, while the other said first N+diffusion region connected to said cathode terminal;
• a first P+ diffusion region formed beside one side of said dummy gate with opposite to said first N+ diffusion region formed beside the other side thereof, said first P+ diffusion region connected to an anode terminal;
• a second P+ diffusion region formed between said first N+ diffusion region connected to said cathode terminal and one said shallow trench isolation in said P well, said second P+ diffusion region connected to said cathode terminal;
• and
• a second N+ diffusion region formed between said first P+ diffusion region and one said shallow trench isolation in said N well, said second N+ diffusion region connected to said anode terminal.

A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process, said method comprising:

• providing a semiconductor substrate with a first conductive type;
• forming a plurality of shallow trench isolations in said substrate;
• forming a first well with a second conductive type between one pair of said shallow trench isolations in said substrate;
• forming a MOS-like gate with said first conductive type on said first well;
• forming a dummy gate on said substrate beside said first well;
• forming a first highly doped diffusion region with said first conductive type beside each side of said MOS-like gate in said first well, one said first diffusion region across one portion of said first well and one portion of said substrate and adjacent to one side of said dummy gate, while said first diffusion region with opposite to said first diffusion region across said first well and said substrate connected to an anode terminal;
• and
• forming a second highly doped diffusion region with said second conductive type beside said dummy gate with opposite to said first diffusion region adjacent to said dummy gate, said second diffusion region connected to a cathode terminal.

A lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process, comprising:

• a P type silicon substrate;
• a plurality of shallow trench isolations formed in said substrate;
• a N well and a P well adjacent thereto formed between one pair of said shallow trench isolations in said substrate;
• a dummy gate formed on said P well;
• a P type polysilicon gate formed on said N well and connected to an anode terminal;
• two first P+ diffusion region respectively formed beside each side of said P type polysilicon gate, one said first P+ diffusion region between said P type polysilicon gate and said dummy gate and across one portion of said N well and one portion of said P well, while the other said first P+ diffusion region connected to said anode terminal;
• two first N+ diffusion region respectively formed beside one side of said dummy gate with opposite to said first P+ diffusion region formed beside the other side thereof, said first N+ diffusion region connected to a cathode terminal;
• a second P+ diffusion region formed between said first N+ diffusion region connected to said cathode terminal and one said shallow trench isolation in said P well, said second P+ diffusion region connected to said cathode terminal;
• and
• a second N+ diffusion region formed between said first P+ diffusion region and one said shallow trench isolation in said N well, said second N+ diffusion region connected to said anode terminal.