Method of forming a dual-gated semiconductor-on-insulator device

A method of forming a dual gated transistor comprising:

• providing a semiconductor-on-insulator (SOI) substrate;
• forming a first transistor gate structure overlying a first side of the semiconductor layer of the SOI substrate, the gate structure comprising opposing sidewalls;
• forming a first spacer adjacent each of the opposing sidewalls;
• forming a source/drain (S/D) contact opening through the semiconductor layer and into the insulator layer of the SOI substrate adjacent each of the first spacers;
• filling the S/D contact openings with a first material;
• exposing the insulator layer overlying a second side of the semiconductor layer, the second side opposing the first side;
• removing the insulator layer disposed between the filled S/D contact openings, the removing exposing at least a portion of the semiconductor layer therebetween and at least one sidewall of each filled S/D contact opening;
• forming a second spacer adjacent each of the exposed sidewalls of each filled S/D contact opening;
• and
• forming a second transistor gate structure over the exposed portion of the semiconductor layer, the second gate being aligned between each of the second spacers.

A method of forming a dual gated semiconductor-on-insulator (SOI) transistor, sequentially comprising:

• providing an SOI substrate comprising a device layer overlying a first side of a buried oxide layer and bulk semiconductive substrate material therebeneath;
• forming a first transistor gate structure disposed over a first side of the device layer;
• forming first sidewall spacers adjacent laterally opposing sidewalls of the first transistor gate structure;
• forming source/drain (S/D) regions within the device layer, the S/D regions being operably adjacent the first transistor gate structure;
• forming a first insulating layer overlying the first transistor gate structure, the first sidewall spacers and the device layer, the first insulating layer having a non-planar upper surface;
• forming S/D contact openings in the first insulating layer and extending through the device layer and through the first side of the buried oxide layer, the S/D contact openings being proximate the first transistor gate structure, a first portion of each S/D contact opening being adjacent each first sidewall spacer and a second portion of each S/D contact opening being within the device layer and extending therefrom through the first side of the buried oxide layer;
• filling the S/D contact openings with a conductive material to form S/D contact structures, a first portion of the S/D contact structures corresponding to the first portion of the S/D contact openings and a second portion of the S/D contact structures corresponding to the second portion of the S/D contact openings;
• planarizing the conductive material and the upper surface of the first insulating layer, the planarizing isolating each S/D contact structure from another S/D contact structure and forming S/D upper surfaces coplanar with the planarized upper surface of the first insulating layer;
• forming a second insulating layer overlying the first insulating layer;
• forming a via contact opening extending through the second insulating layer, the via contact opening exposing at least one of the S/D contact structures;
• filling the via contact opening with a conductive material to form a via contact structure in electrical contact with the exposed S/D contact;
• forming a third insulating layer overlying the second insulating layer;
• bonding a handle wafer to the third insulating layer;
• exposing the S/D contact structures and a second side of the buried oxide layer opposing the first side of the buried oxide layer;
• removing at least a portion of the exposed buried oxide layer disposed between the S/D contact structures effective to expose a portion of a second side of the device layer therebetween and exposing at least one sidewall of each S/D contact structure;
• forming a second spacer adjacent the exposed sidewalls of each S/D contact structure;
• and
• forming a second transistor gate structure over the exposed portion of the second side of the device layer, the second transistor gate structure self-aligning to the first transistor gate structure.