Stacked-gate flash memory and the method of making the same

A method of manufacturing a stacked-gate flash memory, comprising:

• forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric;
• forming a first conductive layer on said first dielectric layer;
• patterning said first dielectric layer, said first conductive layer and said substrate to form a trench in said substrate;
• forming an isolation into said trench;
• removing a portion of said isolation to a surface of said first conductive layer;
• removing a portion of said first conductive layer, thereby forming a cavity between two of said isolation;
• forming a second conductive layer along a surface of said cavity and said isolation;
• removing a portion of said second conductive layer to a surface of said isolation, wherein said second conductive layer and said first conductive layer act as a floating gate;
• forming a second dielectric layer on a surface of said floating gate;
• and
• forming a third conductive layer on said second dielectric layer as a control gate.