Semiconductor memory device capable of adjusting phase of output data and memory system using the same

A memory system comprising:

• a clock generating circuit for generating a system clock signal;
• a controller for receiving a data signal synchronously with said system clock signal;
• and
• a plurality of semiconductor memory devices for outputting said data signal to said controller in accordance with said system clock signal,
• each of said plurality of semiconductor memory devices including an internal clock generating circuit for outputting a first internal clock signal synchronously with said system clock signal,
• said internal clock generating circuit adjusting a phase difference between said system clock signal and said first internal clock signal in accordance with a set value supplied, and
• each of said plurality of semiconductor memory devices further including
• a memory array including a plurality of memory cells for holding said data, and
• an output buffer circuit for outputting, as said data signal, said data read from said memory array synchronously with said first internal clock signal.

A memory module comprising a plurality of semiconductor memory devices for outputting a data signal synchronously with a system clock signal,

• each of said plurality of semiconductor memory devices including an internal clock generating circuit for outputting a first internal clock signal synchronously with said system clock signal,
• said internal clock generating circuit for adjusting a phase difference between said system clock signal and said first internal clock signal in accordance with a set value supplied, and
• each of said plurality of semiconductor memory devices further including
• a memory array including a plurality of memory cells for holding data, and
• an output buffer circuit for outputting, as said data signal, said data read from said memory array synchronously with said first internal clock signal.