Current saving semiconductor memory and method

A semiconductor memory comprising:

• a memory array configured to include a plurality of memory cells;
• a bit line pair configured to input and output complementary data to and from each of the memory cells;
• a pre-charge circuit configured to pre-charge the bit line pair when data reading is performed;
• a sense amplifier configured to amplify a potential difference of the bit line pair;
• a dummy memory circuit configured to simulate dummy data reading from an applicable dummy memory cell when the data reading is performed, said dummy memory circuit including a plurality of dummy memory cells configured to be simultaneously selected together with a corresponding memory cell for reading, said dummy memory cells including pre-fixed complementary data;
• a dummy bit line pair connected to each of the dummy memory cells;
• a dummy sense amplifier configured to amplify a potential difference of the dummy bit line pair, said dummy sense amplifier outputting a control signal for controlling the semiconductor memory when said potential difference of the dummy bit line pair is at a prescribed level;
• a dummy pre-charge circuit configured to pre-charge the dummy bit line pair when the data reading is performed;
• and
• a potential lowering circuit disposed between one of the lines of said dummy bit line pair and the dummy sense amplifier and configured to lower a potential of the one of the lines of the dummy bit line pair so as to temporary create a prescribed difference in potential of the dummy bit line pair.

A semiconductor memory comprising:

• a memory array configured to include a plurality of memory cells;
• at least one bit line pair configured to input and output a complementary signal to and from a prescribed memory cell;
• at least one word line configured to convey an activation control signal to at least one applicable memory cell;
• a pre-charge circuit configured to pre-charge a prescribed bit line pair when data reading is performed;
• a sense amplifier configured to amplify a potential difference of the bit line pair when data reading is performed from an applicable memory cell;
• a write buffer configured to write data to an applicable memory cell via an applicable bit line pair when data writing is performed;
• a dummy memory cell array configured to include a plurality of dummy memory cells each having substantially the same configuration as a corresponding memory cell and connected thereto via a word line, said dummy memory cell array simulating both reading and writing to and from the dummy memory cell;
• a dummy bit line pair configured to input and output a complementary signal to and from an applicable dummy memory cell;
• a dummy write buffer configured to simulate data writing to an applicable dummy memory cell;
• a dummy pre-charge circuit configured to equally pre-charge the dummy bit line pair;
• a dummy memory circuit configured to simulate data reading from a dummy memory cell;
• a potential condition detecting circuit configured to detect a potential of one of the lines of the dummy bit line pair;
• and
• a control section configured to determine the pre-charge condition based upon the detected potential and control the pre-charge circuit and the dummy pre-charge circuit to start operating.