Circuit for synchronizing signals during the exchange of information between circuits

A configuration for synchronizing signals during an exchange of information between circuits of a circuit system, the configuration comprising:

• a delay locked loop circuit for synchronizing an internal clock of one of the circuits and an external clock of the circuit system according to a phase difference between the internal clock and the external clock in a manner dependent on phase changes in the signals, said delay locked loop circuit having a filter for defining a response sensitivity of the delay locked loop circuit, said filter enabling a renewed synchronization only after an arrival of a plurality of phase change events, said filter having a variable configuration and includes:
• a plurality of counters for generating a synchronization enable signal;
• and
• a logic circuit connected to and activating/deactivating said counters.