Non-binary digital logic element and circuit design therefor

A digital logic circuit, comprising a plurality of digital logic elements, each having at least one input and at least one output, each input and each output being able to assume any one of a group of three logic states, comprising a first state (0), a second state (1), and third state (2), and wherein a logic operation relates said logic states at said at least one input to said logic states at said at least one output, the logic elements being any one of a group comprising:

• a first digital logic element for carrying out a logical operation, the element having one input (A) and one output (B), said logical operation being substantially defined by the following table:
• 60 Input A Output B 0 2 1 0 2 1
• a second digital logic element for carrying out a logical operation, the element having a first input (A), a second input (B), and one output (C), said logical operation being substantially defined by the following table:
• 61 Input A Input B Output C 0 0 0 0 1 0 0 2 0 1 0 0 1 1 1 1 2 2 2 0 0 2 1 2 2 2 2
• a third digital logic element for carrying out a logical operation, the element having a first input (A), a second input (B), and one output (C), said logical operation being substantially defined by the following table:
• 62 Input A Input B Output C 0 0 0 0 1 1 0 2 2 1 0 1 1 1 1 1 2 2 2 0 2 2 1 2 2 2 2
• a fourth digital logic element for carrying out a logical operation, the element having a first input (A), a second input (B), and one output (C), said logical operation being substantially defined by the following table:
• 63 Input A Input B Output C 0 0 0 0 1 0 0 2 0 1 0 0 1 1 1 1 2 1 2 0 0 2 1 1 2 2 2
• a fifth digital logic element for carrying out a logical operation, the element having a first input (A), a second input (B), and one output (C), said logical operation being substantially defined by the following table:
• 64 Input A Input B Output C 0 0 0 0 1 1 0 2 2 1 0 1 1 1 1 1 2 1 2 0 2 2 1 1 2 2 2
• a sixth digital logic element for carrying out a logical operation, the element having a first input (A), a second input (B), a third input (Carryin), a first output (Sum), and a second output (Carryout), said logical operation being substantially defined by the following table:
• 65 Carryin Input A Input B Sum Carryout 0 0 0 0 0 0 0 1 1 0 0 0 2 2 0 0 1 0 1 0 0 1 1 2 0 0 1 2 0 1
• 66 Carryin Input A Input B Sum Carryout 0 2 0 2 0 0 2 1 0 1 0 2 2 1 1 1 0 0 1 0 1 0 1 2 0 1 0 2 0 1 1 1 0 2 0 1 1 1 0 1 1 1 2 1 1 1 2 0 0 1 1 2 1 1 1 1 2 2 2 1 2 0 0 2 0 2 0 1 0 1 2 0 2 1 1 2 1 0 0 1 2 1 1 1 1 2 1 2 2 1 2 2 0 1 1 2 2 1 2 1 2 2 2 0 2
• a seventh digital logic element for carrying out a logical operation, the element having a first input (A), a second input (B), and an output (C), said logical operation being substantially defined by the following table:
• 67 Input A Input B Output C 0 0 2 0 1 0 0 2 1 1 0 0 1 1 0 1 2 1 2 0 1 2 1 1 2 2 1
• an eighth digital logic element for carrying out a logical operation, the element having a first input (A), a second input (B), a third input (C), a first output (D), a second output (E), and a third output (F), said logical operation being substantially defined by the following table:
• 68 Previous Next Outputs Outputs Input A Input B Input C (D, E, F) (D, E, F) 0 0 0 (0, 1, 2) (0, 1, 2) 0 0 0 (1, 2, 0) (1, 2, 0) 0 0 0 (2, 0, 1) (2, 0, 1) 0 0 1 (0, 1, 2) (0, 1, 2) 0 0 1 (1, 2, 0) (1, 2, 0) 0 0 1 (2, 0, 1) (0, 1, 2) 0 0 2 (1, 2, 0) 0 1 0 (0, 1, 2) (0, 1, 2)
• 69 Previous Next Outputs Outputs Input A Input B Input C (D, E, F) (D, E, F) 0 1 0 (1, 2, 0) (2, 0, 1) 0 1 0 (2, 0, 1) (2, 0, 1) 0 1 1 (0, 1, 2) 0 1 2 (1, 0, 0) 0 2 0 (0, 1, 2) 0 2 1 (0, 1, 2) 0 2 2 (1, 1, 0) 1 0 0 (0, 1, 2) (1, 2, 0) 1 0 0 (1, 2, 0) (1, 2, 0) 1 0 0 (2, 0, 1) (2, 0, 1) 1 0 1 (1, 2, 0) 1 0 2 (1, 2, 0) 1 1 0 (2, 0, 1) 1 1 1 (0, 0, 0) 1 1 2 (1, 0, 0) 1 2 0 (0, 1, 0) 1 2 1 (0, 1, 0) 1 2 2 (1, 1, 0) 2 0 0 (2, 0, 1) 2 0 1 (0, 0, 1) 2 0 2 (1, 0, 1) 2 1 0 (2, 0, 1)
• 70 Previous Next Outputs Outputs Input A Input B Input C (D, E, F) (D, E, F) 2 1 1 (0, 0, 1) 2 1 2 (1, 0, 1) 2 2 0 (0, 1, 1) 2 2 1 (0, 1, 1) 2 2 2 (1, 1, 1)
• a ninth digital logic element for carrying out a logical operation, the element having a first input (A), a second input (Clock), and one output (Out1), said logical operation being substantially defined by the following table:
• 71 Input A Clock Out1 0 Trigger 0 1 Trigger 1 2 Trigger 2 Any value 0 Unchanged
• a tenth digital logic element for carrying out a logical operation, the element having a first input (A), a second input (Clock), a third input (Set0), a fourth input (Set1), a fifth input (Set2), a first output (Out1), a second output (Out2), and a third output (Out3), wherein said second input repetitively undergoes a cycle comprising a first and a second transition, and wherein said tenth logical operation is substantially defined by the following table:
• 72 Input A Clock Out1 Out2 Out3 0 First 2 0 1 transition 1 First 0 1 2 transition 2 First 1 2 0 transition Any value 0 Unchanged Unchanged Unchanged
• and wherein the value of the outputs can be set while the clock is at 0 by applying signals at Set0, Set1, and Set2, substantially according to the following table:
• 73 Input A Clock Set0 Set1 Set2 Out1 Out2 Out3 X 0 2 0 0 2 0 1 X 0 0 2 0 0 1 2 X 0 0 0 2 1 2 0;
• and, an eleventh digital logic element for carrying out a logical operation, the element having one input (A) and one output (B), said logical operation being substantially defined by the following table:
• 74 Input A Output B 0 1 1 2 2 0

A method for designing a digital logic circuit to implement a truth table, relating the state of at least one input to the state of an output, each input and each output being capable of assuming at least three logic states, comprising a first state (0), a second state (1), and a third state (2) , the method comprising:

• providing a predetermined truth table having a plurality of rows relating input states to corresponding output states;
• identifying each line of the table in which the output state is non-zero;
• expressing each thus identified line of the table as a combination of AND and NOT operations on the inputs, so that for the given input values the result of the said operations is the value of the output as given in said table, and for all other input values the result is zero;
• and,
• using said corresponding outputs as inputs to a multi-input OR operation, wherein if all inputs are 0 the output is 0, if the inputs contain 1's but no 2's the output is 1, and if the inputs contain 2's the output is 2, thereby producing a first relationship between said input states and said output states.

A method for building a digital logic circuit to implement a truth table, relating the state of at least one input to the state of an output, each input and each output being capable of assuming at least three logic states, comprising a first state (0), a second state (1), and a third state (2), the method comprising:

• providing a predetermined truth table having a plurality of rows relating input states to corresponding output states;
• identifying each line of the table in which the output state is non-zero;
• expressing each thus identified line of the table as a combination of AND and NOT operations on the inputs, so that for the given input values the result of the said operations is the value of the output as given in said table, and for all other input values the result is zero;
• using said corresponding outputs as inputs to a multi-input OR operation, wherein if all inputs are 0 the output is 0, if the inputs contain l's but no 2's the output is 1, and if the inputs contain 2's the output is 2, thereby producing a first relationship between said input states and said output states;
• and,
• building a 3-state logic circuit by connecting 3-state logic AND, OR, and NOT gates according to said first relationship.

A method for building a digital logic circuit to implement a truth table, relating the state of at least one input to the state of an output, each input and each output being capable of assuming at least three logic states, comprising a first state (0), a second state (1), and a third state (2), the method comprising:

• providing a predetermined truth table having a plurality of rows relating input states to corresponding output states;
• identifying each line of the table in which the output state is non-zero;
• expressing each thus identified line of the table as a combination of AND and NOT operations on the inputs, so that for the given input values the result of the said operations is the value of the output as given in said table, and for all other input values the result is zero;
• using said corresponding outputs as inputs to a multi-input OR operation, wherein if all inputs are 0 the output is 0, if the inputs contain 1's but no 2's the output is 1, and if the inputs contain 2's the output is 2, thereby producing a first relationship between said input states and said output states;
• reducing the number of inputs and variable in the resulting expression by use of at least one of the following logical expressions:
• X+X=X,
• X*X=X,
• X+Y=Y+X,
• X*Y=Y*X,
• X+0=X,
• X*1=X,
• X*0=0,
• X+2=2,
• X*(Y+Z)=X*Y+X*Z,
• X*(Y*Z)=(X*Y)*Z,
• X+(Y+Z)=(X+Y)+Z,
• X*(Y+1)=X*Y+X,
• (X*Y*Z* . . . )#=X#+Y#+Z# . . . , and
• (X+Y+Z+ . . . )##=X##*Y##*Z## . . . ,
• thereby producing a second reduced relationship between said input states and said output states;
• and,
• building a 3-state logic circuit by connecting 3-state logic AND, OR, and NOT gates according to said second relationship.

A method for automatically designing a digital logic circuit to implement a truth table, relating the state of at least one input to the state of an output, each input and each output being capable of assuming at least three logic states, comprising a first state (0), a second state (1), and a third state (2), comprising:

• providing a predetermined truth table having a plurality of rows relating input states to corresponding output states;
• automatically designing a circuit by:
• identifying each line of the table in which the output state is non-zero;
• expressing each thus identified line of the table as a combination of AND and NOT operations on the inputs, so that for the given input values the result of the said operations is the value of the output as given in said table, and for all other input values the result is zero;
• using said corresponding outputs as inputs to a multi-input OR operation, wherein if all inputs are 0 the output is 0, if the inputs contain 1's but no 2's the output is 1, and if the inputs contain 2's the output is 2, thereby producing a first relationship between said input states and said output states;
• and;
• reducing the number of inputs and variable in the resulting expression by use of at least one of the following logical expressions:
• X+X=X,
• X*X=X,
• X+Y=Y+X,
• X*Y=Y*X,
• X+0=X,
• X*1=X,
• X*0=0,
• X+2=2,
• X*(Y+Z)=X*Y+X*Z,
• X*(Y*Z)=(X*Y)*Z,
• X+(Y+Z)=(X+Y)+Z,
• X*Y+X=X*(Y+1),
• X#+Y# . . . =(X*Y*Z* . . . )#, and
• X##Y##Z# . . . =(X+Y+Z+ . . . )##,
• thereby producing a second reduced relationship between said input states and said output states;
• simulating the circuit designated by said second relationship;
• and, verifying that for every combination of inputs the circuit provides the specified output.

A method of building non-binary digital circuitry, comprising the steps of:

• selecting a base for non-binary digital operation;
• defining each of AND, and OR operations in said base;
• defining a cyclic NOT operation in said base, wherein if the input to said NOT operation is cyclic the output is cyclic;
• testing the system to determine if it possesses at least one of a group of characteristics comprising:
• possession of a zero member,
• possession of a one member,
• obeys the Idempotent Law,
• obeys the Commutative Law, and
• obeys the DeMorgan Laws;
• if the system does not possess at least one of the characteristics, then redefining said operations until a fit is achieved;
• and,
• building at least one logic gate according to the defined operations.

A method for building a digital logic circuit to implement a truth table, relating the state of at least one input to the state of an output, each input and each output being capable of assuming at least three logic states, comprising a first state (0), a second state (1), and a third state (2), the method comprising:

• providing a predetermined truth table having a plurality of rows relating input states to corresponding output states;
• identifying each line of the table in which the output state is non-zero;
• expressing each thus identified line of the table as a combination of AND and NOT operations on the inputs, so that for the given input values the result of the said operations is the value of the output as given in said table, and for all other input values the result is zero;
• using said corresponding outputs as inputs to a multi-input OR operation, wherein if all inputs are 0 the output is 0, if the inputs contain 1's but no 2's the output is 1, and if the inputs contain 2's the output is 2, thereby producing a first relationship between said input states and said output states;
• reducing the number of inputs and variable in the resulting expression by use of at least one of the following characteristics:
• possession of a zero member,
• possession of a one member,
• the Idempotent Law,
• the Associative Law,
• the Identity Laws,
• the Dominance Laws,
• the Complement Laws,
• the Distributive Law,
• the Commutative Law, and
• the DeMorgan Laws,
• thereby producing a second reduced relationship between said input states and said output states;
• and,
• building a 3-state logic circuit by connecting 3-state logic AND, OR, and NOT gates according to said second relationship.

A method for automatically designing a digital logic circuit to implement a truth table, relating the state of at least one input to the state of an output, each input and each output being capable of assuming at least three logic states, comprising a first state (0), a second state (1), and a third state (2), comprising:

• providing a predetermined truth table having a plurality of rows relating input states to corresponding output states;
• automatically designing a circuit by:
• identifying each line of the table in which the output state is non-zero;
• expressing each thus identified line of the table as a combination of AND and NOT operations on the inputs, so that for the given input values the result of the said operations is the value of the output as given in said table, and for all other input values the result is zero;
• using said corresponding outputs as inputs to a multi-input OR operation, wherein if all inputs are 0 the output is 0, if the inputs contain l's but no 2's the output is 1, and if the inputs contain 2's the output is 2, thereby producing a first relationship between said input states and said output states;
• and;
• reducing the number of inputs and variable in the resulting expression by use of at least one of the following characteristics:
• possession of a zero member,
• possession of a one member,
• the Idempotent Law,
• the Associative Law,
• the Identity Laws,
• the Dominance Laws,
• the Complement Laws,
• the Distributive Law,
• the Commutative Law, and
• the DeMorgan Laws,
• thereby producing a second reduced relationship between said input states and said output states;
• simulating the circuit designated by said second relationship;
• and,
• verifying that for every combination of inputs the circuit provides the specified output.