Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure

A wiring structure for use in a semiconductor integrated circuit, comprising:

• a semiconductor substrate;
• an underlying dielectric layer formed over the semiconductor structure;
• a wiring layer, including at least two adjacent wires, formed on the underlying dielectric layer;
• and
• a dielectric layer, the dielectric layer having an underlying film, the underlying film having a dielectric constant lower than that of silicon oxide, the underlying film being formed at least on opposing side surfaces of the at least two adjacent wires, and a low dielectric constant film having a dielectric constant lower than that of the underlying film, the low dielectric constant film being formed at least between the opposing side surfaces of the adjacent wires.

A wiring structure for use in a semiconductor integrated circuit, comprising:

• a semiconductor substrate;
• an underlying dielectric layer;
• a wiring layer, including at least two adjacent wires, formed on the underlying dielectric layer;
• and
• a dielectric layer, including an underlying film formed at least on opposing side surfaces of the at least two adjacent wires, and a low dielectric constant film, the low dielectric constant film having a dielectric constant lower than that of silicon oxide, the low dielectric constant film formed at least between the opposing side surfaces of the at least two adjacent wires, such that the opposing side surfaces of the at least two adjacent wires are substantially vertical to a main surface of the semiconductor substrate, and surfaces of the underlying film on the opposing side surfaces are positively sloped.

A method of forming a wiring structure for use in a semiconductor integrated circuit, comprising the steps of:

• forming a wiring layer, including at least two adjacent wires, on an underlying dielectric layer over a semiconductor substrate;
• and
• forming a dielectric layer, including forming an underlying film, at least on opposing side surfaces of the at least two adjacent wires, and forming a low dielectric constant film having a dielectric constant lower than that of silicon oxide at least between the opposing side surfaces of the adjacent wires,
• wherein the opposing side surfaces of the adjacent wires are substantially vertical to a main surface of the semiconductor substrate, and surfaces of the underlying film on the opposing side surfaces are positively sloped.

A wiring structure for use in a semiconductor integrated circuit, comprising:

• a semiconductor substrate;
• an underlying dielectric layer;
• a wiring layer, including at least two adjacent wires having opposing side surfaces, the wiring layer formed on the underlying dielectric layer;
• and
• a dielectric layer, including an underlying film formed at least on the opposing side surfaces of the adjacent wires and a low dielectric constant film having a dielectric constant lower than that of silicon oxide, formed at least between the at least two adjacent wires,
• wherein a thickness of the underlying film on upper portions of the opposing side surfaces of the adjacent wires is smaller than that on lower portions of the opposing side surfaces.

A method of forming a wiring structure for use in a semiconductor integrated circuit, comprising the steps of:

• forming a wiring layer, including at least two adjacent wires, on an underlying dielectric layer formed over a semiconductor substrate;
• and
• forming a dielectric layer, including forming an underlying film at least on opposing side surfaces of the at least two adjacent wires, and forming a low dielectric constant film having a dielectric constant lower than that of silicon oxide at least between the adjacent wires,
• wherein a thickness of the underlying film on upper portions of the opposing side surfaces of the adjacent wires is smaller than that on lower portions of the opposing side surfaces.

A wiring structure for use in a semiconductor integrated circuit, comprising:

• an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than that of silicon oxide, formed over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film, the groove having side walls;
• side wall films having a second dielectric constant lower than that of silicon oxide, the side wall films formed on the side walls of the groove;
• and
• a wiring layer, including a wire formed in the groove.

A method of forming a wiring structure for use in a semiconductor integrated circuit, comprising the steps of:

• forming an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than that of silicon oxide over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film;
• forming side wall films having a second dielectric constant that is lower than that of silicon oxide, the side wall films formed on side walls of the groove;
• and
• forming a wiring layer, including a wire formed in the groove.

A wiring structure for use in a semiconductor integrated circuit, comprising:

• an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than that of a silicon oxide, formed over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film, the groove having side walls;
• side wall films formed on side walls of the groove;
• and
• a wiring layer, including a wire formed in the groove,
• wherein the side walls of the groove are substantially vertical with respect to a main surface of the semiconductor substrate and surfaces of the side wall films are positively sloped.

A method of forming a wiring structure for use in a semiconductor integrated circuit, comprising the steps of:

• forming an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than a dielectric constant of silicon oxide, over a surface of the semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film;
• forming side wall films on side walls of the groove;
• and
• forming a wiring layer, including a wire in the groove,
• wherein the side walls of the groove are substantially vertical with respect to a main surface of the semiconductor substrate, and surfaces of the side wall films are positively sloped.

A wiring structure for use in a semiconductor integrated circuit, comprising:

• a semiconductor substrate;
• an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than that of silicon oxide, formed over the semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film, the groove having side walls;
• side wall films formed on the side walls of the groove;
• and
• a wiring layer, including a wire formed in the groove,
• wherein a thickness of the side wall films on upper portions of the side walls of the groove is smaller than that on lower portions of the side walls.

A method of forming a wiring structure for use in a semiconductor integrated circuit, comprising the steps of:

• forming an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than that of silicon oxide, over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film;
• forming side wall films on side walls of the groove;
• and
• forming a wiring layer, including a wire in the groove,
• wherein a thickness of the side wall films on upper portions of the side walls of the groove is smaller than that on lower portions of the side walls.

A semiconductor integrated circuit, comprising:

• a semiconductor substrate;
• at least one aluminum-based wiring layer disposed over the semiconductor substrate;
• at least one low resistance wiring layer disposed over the at least one aluminum-based wiring layer;
• and
• at least one circuit block, including a plurality of transistors disposed on the semiconductor substrate, the plurality of transistors being connected with each other by wires on the at least one aluminum-based wiring layer,
• wherein wires of a selected type of wiring are formed on the at least one low resistance wiring layer.

A semiconductor integrated circuit, comprising:

• a semiconductor substrate;
• at least one aluminum-based wiring disposed over the semiconductor substrate;
• at least one low resistance wiring layer disposed over the at least one aluminum-based wiring layer;
• and
• at least one macro cell, which has been designed and verified without using a low resistance wiring.

An application specific semiconductor integrated circuit of one of a first and a second grade, comprising:

• at least one macro cell selected from a macro cell library commonly provided for the first and the second grade;
• and
• at least one aluminum-based wiring layer,
• wherein the semiconductor integrated circuit further includes at least one low resistance wiring layer only when the grade is a preselected one.

A method of designing an application specific semiconductor integrated circuit of one of a first and a second grade, comprising the steps of:

• selecting at least one macro cell from a macro cell library commonly provide for the first and the second grade;
• and
• placing the selected macro cell on the semiconductor integrated circuit chip,
• wherein the method further includes, only when the grade is a preselected one, the step of making connections outside of the macro cell by using wires on at least one low resistance wiring layer.