US 2002/0158281 A1 · Stress-reduced layer system

Abstract

The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

Claims35

Dependent claims

A storage capacitor, comprising:

a lower capacitor electrode;
a storage dielectric;
and
an upper capacitor electrode;
at least one of said lower and upper capacitor electrodes being a conductive layer;
a doped layer selected from the group consisting of a SiGe layer, a SiC layer, and a GaAs layer or a doped filling selected from the group consisting of a SiGe filling, a SiC filling, and a GaAs filling disposed between said conductive layer and said storage dielectric;
and
wherein a doped SiGe layer is not disposed between said storage dielectric and said upper capacitor electrode.

5 more elements

Dependencies are inferred from the claim text.

Stress-reduced layer system

Life of this patent

Stress-reduced layer system

Life of this patent

Abstract

Claims35