Fuse read sequence for auto refresh power reduction
AssigneeMicron Technology, Inc.
InventorGreg A. Blodgett
Life of this patent
Estimating the term…
Abstract
A fuse read sequence for a memory device obtains enhanced energy efficiency by selectively reading or strobing antifuse or fuse circuit banks of the memory device in response to operational commands of the memory device. More particularly, the column antifuse circuit banks of a SDRAM are read in response to a load mode register command and the row and option antifuse circuit banks are read in response to auto refresh commands. Furthermore, only half of the row/option antifuse circuit banks are read on each auto refresh command.
Claims22
A method of reading antifuses in a memory device comprising:
- reading a first set of antifuses in response to a first command;
- and
- reading a second set of antifuses in response to a second command.
A method for reading antifuse circuits in a memory device comprising:
- generating a command signal;
- interpreting said command signal;
- generating a read signal in response to said command signal;
- applying said read signal to read selected antifuse circuits in said memory device;
- and
- terminating said read signal.
A fuse read signal toggle circuit comprising:
- a fuse read signal input for receiving a fuse read signal;
- a delay flip-flop comprising a clock operably connected to said fuse read signal input, a delay flip-flop input, a first delay output, and a second delay output operably connected to said delay flip-flop input;
- a first AND gate operably coupled to said fuse read signal input and said first delay output, said first AND gate also having a first AND gate output for conducting a first fuse read signal;
- and
- a second AND gate operably coupled to said fuse read signal input and said second delay output, said second AND gate also having a second AND gate output for conducting a second fuse read signal.
A computer system comprising:
- a processor;
- a memory controller coupled to said processor;
- and
- a memory device coupled to said processor through said memory controller, said memory device configured for reading a first set of antifuses in response to a first command and a second set of antifuses in response to a second command.
Dependencies are inferred from the claim text.