Layered dielectric on silicon carbide semiconductor structures

A dielectric structure for silicon carbide semiconductor devices, said dielectric structure comprising:

• a portion of silicon carbide;
• a layer of silicon dioxide on said silicon carbide portion;
• a layer of silicon nitride on said silicon dioxide layer, and
• a second layer of silicon dioxide on said silicon nitride layer.

A method of producing a silicon carbide insulated gate device that is particularly suited for high power, high field or high temperature operation, the method comprising:

• forming a layer of silicon dioxide on a portion of silicon carbide;
• forming a layer of an insulating material other than silicon dioxide and with a dielectric constant higher than the dielectric constant of silicon dioxide on the silicon dioxide layer;
• and
• depositing a gate contact on the layer of insulating material.

A method of producing a silicon carbide insulated gate device that is particularly suited for high power, high field or high temperature operation, the method comprising:

• thermally oxidizing a portion of silicon carbide to thereby form a layer of silicon dioxide on the silicon carbide portion;
• depositing a layer of an insulating material other than silicon dioxide and with a dielectric constant higher than the dielectric constant of silicon dioxide on the silicon dioxide layer;
• forming a second layer of silicon dioxide on the layer of the high dielectric insulating material;
• and
• thereafter depositing a gate contact on the second silicon dioxide layer.

An insulated gate field effect transistor (IGFET) that is particularly suitable for high power applications, said IGFET comprising:

• a first silicon carbide portion having a first conductivity type;
• a gate insulator on said first conductivity type silicon carbide portion, said gate insulator including a layer of silicon dioxide on said first silicon carbide portion, and a layer of another insulating material on said silicon dioxide layer, said insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide;
• a gate contact to said gate insulator for depleting said first silicon carbide portion when a potential is applied to said gate contact;
• source and drain portions of silicon carbide having the opposite conductivity type from said first silicon carbide portion and with said first silicon carbide portion between said source and drain portions;
• and
• respective ohmic contacts to said source and drain.

An insulated gate field effect transistor (IGFET) that is particularly suitable for high temperature applications, said IGFET comprising:

• a silicon carbide substrate;
• a silicon carbide epitaxial layer on said substrate and having a first conductivity type;
• a gate insulator on said silicon carbide epitaxial layer, said gate insulator including a first layer of silicon dioxide on said epitaxial layer, a layer of silicon nitride on said first silicon dioxide layer, and a second silicon dioxide layer on said silicon nitride layer;
• a gate contact to said second silicon dioxide layer so that said insulator and gate contact define a channel region in said silicon carbide epitaxial layer;
• respective implanted regions in said silicon carbide epitaxial layer portions adjacent said channel, said implanted regions and having the opposite conductivity type from said channel;
• and
• respective ohmic contacts to said implanted regions for defining a source and drain.

A metal-insulator-semiconductor (MIS) capacitor comprising:

• a doped silicon carbide portion;
• a capacitance insulator portion on said doped silicon carbide portion, said capacitance insulator including a layer of silicon dioxide on said doped silicon carbide portion, and a layer of another insulating material on said silicon dioxide layer, said insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide
• a metal contact to said capacitance insulator portion for defining an active region of said doped silicon carbide portion;
• and
• an ohmic contact to said doped silicon carbide portion so that a bias applied to said metal contact variably depletes said doped silicon carbide portion to correspondingly vary the capacitance of said capacitor.

A metal-insulator-semiconductor (MIS) capacitor that forms the gate portion of an insulated gate device, said MIS capacitor comprising:

• a doped silicon carbide portion;
• a capacitance insulator portion on said doped silicon carbide portion, said capacitance insulator including a first layer of silicon dioxide on said doped silicon carbide portion, a layer of silicon nitride on said first silicon dioxide layer, and a second layer of silicon dioxide on said layer of silicon nitride;
• and
• a metal contact to said capacitance insulator portion for defining an active region of said doped silicon carbide portion.

A U-shaped metal-insulator-semiconductor field-effect transistor (UMISFET) wherein:

• the active portions of said UMISFET are formed of silicon carbide;
• and wherein the gate insulator portion of said UMISFET comprises,
• a layer of silicon dioxide on said silicon carbide layer;
• a layer of another insulating material on said silicon dioxide layer, said insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide;
• and
• a second layer of silicon dioxide on said high dielectric insulating material.

A high power semiconductor device comprising:

• active portions formed of silicon carbide;
• and
• passivation portions that experience high fields under an applied potential;
• wherein said high field passivation portions are formed of,
• a layer of silicon dioxide on a portion of silicon carbide;
• a layer of another insulating material on said silicon dioxide layer, said insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide, and
• a capping layer of silicon dioxide on said high dielectric layer.