Semiconductor devices and methods for manufacturing the same

A semiconductor device comprising:

• an insulation layer;
• a semiconductor layer formed on the insulation layer;
• an element isolation region formed in the semiconductor layer;
• element forming regions defined by the element isolation region;
• and
• a bi-polar transistor and a field effect transistor in at least one of the element forming regions;
• wherein a gate electrode layer is formed on the semiconductor layer,
• the gate electrode layer is formed in a manner to cross over the element forming region,
• a first electrode layer is formed on the semiconductor layer,
• wherein the first electrode layer has one end section continuing to a side section of the gate electrode layer, and another end section reaching the element isolation region,
• a first impurity diffusion layer of the second conduction type is formed in a first region surrounded by the gate electrode layer in the field effect transistor forming region, the first electrode layer and the element isolation region,
• a second impurity diffusion layer of the second conduction type is formed in the field effect transistor forming region among a second region surrounded by the gate electrode layer and the element isolation region,
• a first impurity diffusion layer of the first conduction type is formed in the second region in the bi-polar transistor forming region,
• a second impurity diffusion layer of the first conduction type is formed in a third region surrounded by the gate electrode layer in the bi-polar transistor forming region, the first electrode layer and the element isolation region,
• a first conduction type body region is formed below the gate electrode layer,
• a third impurity diffusion layer of the second conduction type is formed below the gate electrode layer in the bi-polar transistor forming region and the first electrode layer and along a periphery of the second impurity diffusion layer of the first conduction type,
• the first conduction type body region is electrically connected to the first impurity diffusion layer of the first conduction type,
• the second impurity diffusion layer of the second conduction type is electrically connected to the first impurity diffusion layer of the first conduction type, and
• the first impurity diffusion layer of the second conduction type is electrically connected to the third impurity diffusion layer of the second conduction type.

A method for manufacturing a semiconductor device including an insulation layer and a semiconductor layer formed on the insulation layer, the method comprising the steps of:

• (A) forming an element isolation region in the semiconductor layer to define element forming regions;
• and
• (B) forming a field effect transistor and a bi-polar transistor in the same one of the element forming regions,
• wherein the step (B) comprises the steps of:
• (B-1) forming a first conduction type body region at least in the semiconductor layer in a forming region where a gate electrode layer is to be formed;
• (B-2) forming a first body region of a second conductivity type at least in a part of the semiconductor layer in a forming region where a first layer is to be formed;
• (B-3) forming the gate electrode layer and the first electrode layer on the semiconductor layer, wherein the first electrode layer has one end section that continues to a side section of the gate electrode layer and another end section that reaches the element isolation region;
• (B-4) forming an impurity diffusion layer of the second conduction type in the semiconductor layer in a third region surrounded by the gate electrode layer in the bi-polar transistor forming region, the first electrode layer and the element isolation region;
• (B-5) conducting a thermal treatment to thermally diffuse the impurity diffusion layer of the second conduction type to form a base region of the bi-polar transistor below the gate electrode layer and below the first electrode layer in the semiconductor layer,
• (B-6) forming a drain region of the second conduction type of the field effect transistor in a first region surrounded by the gate electrode layer of the field effect transistor, the first electrode layer and the element isolation region, wherein the drain region is electrically connected to the base region through the first body region of the second conduction type;
• (B-7) forming a source region of the second conduction type of the field effect transistor in a part of a second region surrounded by the gate electrode layer and the element isolation region;
• (B-8) forming a collector region of the first conduction type of the bi-polar transistor in a part of the second region, wherein the collector region is electrically connected to the first conduction type body region;
• (B-9) forming an emitter region of the first conduction type of the bi-polar transistor in the third region;
• and
• (B-10) electrically connecting the source region and the collector region.

A method for manufacturing a semiconductor device including an insulation layer and a semiconductor layer formed on the insulation layer, the method comprising the steps of:

• (A) forming an element isolation region in the semiconductor layer to define element forming regions;
• and
• (B) forming a field effect transistor and a bi-polar transistor in the same one of the element forming regions,
• wherein the step (B) comprises the steps of:
• (B-1) forming a first conduction type body region in the semiconductor layer at least in a forming region where a gate electrode layer is to be formed and in a forming region where a second layer is to be formed;
• (B-2) forming a first body region of the second conductivity type at least in a part of the semiconductor layer in a forming region where a first layer is to be formed;
• (B-3) forming a gate electrode layer on the semiconductor layer;
• (B-4) forming a first layer on the semiconductor layer, wherein the first layer has one end section that continues to the gate electrode layer or the second layer and another end section that reaches the element isolation region;
• (B-5) forming a second layer on the semiconductor layer,
• wherein the second layer has one end section that continues to the gate electrode layer or the first layer and another end section that reaches the element isolation region;
• (B-6) forming an impurity diffusion layer of the second conduction type in the semiconductor layer in a third region surrounded by the first layer, the second layer and the element isolation region;
• (B-7) conducting a thermal treatment to thermally diffuse the impurity diffusion layer of the second conduction type to form a base region of the second conduction type of the bi-polar transistor below the first layer and in the semiconductor layer below the second layer,
• (B-8) forming a drain region of the second conduction type of the field effect transistor in a first region surrounded by the gate electrode layer, the first layer and the element isolation region, wherein the drain region is electrically connected to the base region through the first body region of the second conduction type;
• (B-9) forming a source region of the second conduction type of the field effect transistor at least in a part of a second region surrounded by the gate electrode layer, the second layer and the element isolation region;
• (B-10) forming a collector region of the first conduction type of the bi-polar transistor in a part of a second region surrounded by the gate electrode layer, the second layer and the element isolation region, wherein the collector region of the first conduction type is electrically connected to the first conduction type body region;
• (B-11) forming an emitter region of the first conduction type of the bi-polar transistor in a third region surrounded by the first layer, the second layer and the element isolation region;
• and
• (B-12) electrically connecting the source region and the collector region.

A method for manufacturing a semiconductor device comprising:

• providing a semiconductor layer;
• forming an element isolation region in the semiconductor layer to define element forming regions;
• forming a bi-polar transistor and a field effect transistor in at least one of the element forming regions;
• wherein the bi-polar transistor is formed to include an emitter region of a first conduction type, a base region of a second conduction type, and a collector region of the first conduction type;
• wherein the field effect transistor is formed to includes a gate electrode layer, a source region of the second conduction type, and a drain region of the second conduction type;
• wherein the field effect transistor is further formed to includes a first conduction type body region formed at least between the source region and the drain region;
• and
• electrically connecting the first conduction type body region to the collector region, the source region to the collector region, and the drain region to the base region.