Two-stage ESD protection circuit with a secondary ESD protection circuit having a quicker trigger-on rate
AssigneeVanguard International Semiconductor Corporation
InventorsGeeng-Lih Lin, Ming-Dou Ker
Life of this patent
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Abstract
A two-stage ESD protection circuit coupled between an I/O pad and a power rail is provided in the present invention. The two-stage ESD protection circuit has a primary ESD protection circuit and a secondary ESD circuit. The trigger-on rate of the secondary ESD protection circuit is sped up by employing an ESD detection circuit coupled to the I/O pad. It can be further sped up by employing a native NMOS in the secondary ESD protection. According to the invention, the trigger-on speed of the secondary ESD protection circuit can be effectively improved to obtain better ESD protection for the thinner gate oxides of internal circuits in sub-quarter-micron CMOS process.
Claims15
A two-stage electrostatic discharge (ESD) protection circuit, suitable to an input/output (I/O) port, coupled across a pad and a power rail, comprising:
- a primary ESD protection circuit, coupled between the pad and the power rail;
- an ESD detection circuit, coupled between the pad and the power rail;
- a resistor, connected in series between the pad and a internal circuit;
- and
- a secondary ESD protection circuit, coupled between the internal circuit and the power rail;
- wherein, at the beginning of an ESD event, the ESD detection circuit provide a trigger voltage to trigger on the secondary ESD protection circuit prior to the activation of the primary ESD protection circuit, thereby clamping voltage received by the internal circuit.
A two-stage ESD protection circuit, suitable to an input/output (I/O) port, coupled across a pad and a power rail, comprising:
- a primary ESD protection circuit, coupled between the pad and the power rail, comprising a general NMOS with a first threshold voltage;
- a resistor, connected in series between the pad and an internal circuit;
- and
- a secondary ESD protection circuit, coupled between the internal circuit and the power rail and comprising a native NMOS with a second threshold voltage lower than the first threshold voltage;
- wherein, at the beginning of an ESD event, the native NMOS in the secondary ESD protection circuit is triggered on prior to the activation of the general NMOS in the primary ESD protection circuit, thereby clamping voltage received by the internal circuit.
Dependencies are inferred from the claim text.