Two-transistor flash cell

A method of manufacturing a semiconductor device comprising in a semiconductor substrate (21) containing a first dopant type, a first non-volatile memory cell (20;

• 200) for storing a bit, comprising a first drain region (24) in said substrate (21), a first floating gate (29), a first control gate (30), a buried layer (22) containing a second dopant type and a first source region (26), a first thin gate isolation layer (27), and an insulating layer (32), said insulating layer (32) being positioned on top of said first floating gate (29), said first control gate (30) being positioned on top of said insulating layer (32), said first floating gate (29) being positioned on top of said first thin gate isolation layer (27), said arrangement further comprising a first access transistor (34), and said method comprising the following steps:
• formation of said buried layer (22) in said substrate (21) by ion implantation;
• demarcation of an active area of said non-volatile memory cell (20;
• 200) by the formation of isolation lines (STI) extending in a first direction;
• formation of said first thin gate isolation layer (27) on said surface of said substrate (21);
• formation of a stacked gate structure (29, 30, 32) on top of said first gate isolation layer (27), said stacked gate structure comprising said first floating gate (29), said control gate (30), and said insulating layer (32);
• formation of said first access transistor (34) comprising the following steps:
• etching of a trench in said substrate (21) substantially from its surface to said buried layer (22),
• formation of a second thin oxide (35) on the trench walls,
• deposition of doped polysilicon in said trench, said trench being adjacent to the stacked gate structure (29, 30, 32);
• passivation and metallization of said non-volatile memory cell (20;
• 200).