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US 2002/0120912 A1Published application
Method and apparatus for scalable interconnect solution
AssigneeCadence Design Systems, Inc.
InventorsLimin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
Life of this patent
Estimating the term…
Abstract
An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
Claims69
A method of routing an integrated circuit (IC) design, comprising:
- accessing the IC design including a plurality of objects on one or more layers;
- forming a plurality of levels, wherein the plurality of levels includes a first level representing the IC design at a first grid density, a second level representing the IC design at a second grid density finer than at least the first grid density, and a third level representing the IC design at a third grid density finer than at least the first grid density and the second grid density;
- based at least partly on the IC design, populating each level of the plurality of levels with the plurality of objects;
- and
- interconnecting the objects at one or more of the first level, the second level, and the third level.
2 more elements
A method of routing an integrated circuit (IC) design, comprising:
- accessing the IC design including a plurality of objects on one or more layers;
- accessing a first level for the IC design, wherein the first level of the IC design is partitioned into a first plurality of one or more partitions, and the plurality of objects of the IC design are among the first plurality of one or more partitions;
- and
- forming a second level for the IC design, including:
- partitioning the second level into a second plurality of partitions, wherein one or more partitions of the first plurality of partitions is represented by at least two partitions of the second plurality of partitions;
- and
- within each partition of the second plurality of partitions, interconnecting objects substantially independently of other partitions of the second plurality of partitions.
4 more elements
A method of routing an integrated circuit (IC) design, comprising:
- accessing the IC design including a plurality of objects on one or more layers;
- accessing a first level for the IC design, wherein the first level of the IC design is partitioned into a first plurality of one or more partitions, and the plurality of objects of the IC design are among the first plurality of one or more partitions;
- and
- forming a second level for the IC design, including:
- partitioning the second level into a second plurality of partitions, wherein one or more partitions of the first plurality of partitions is represented by at least two partitions of the second plurality of partitions;
- allotting the second plurality of partitions among a plurality of areas, such that each area of the plurality of areas includes one or more partitions of the second plurality of partitions;
- and
- within each area of the plurality of areas, interconnecting objects substantially independently of other areas of the plurality of areas.
5 more elements
A method of routing an integrated circuit (IC) design, comprising:
- accessing the IC design including a plurality of blockages and a plurality of pins;
- forming a graph including a first plurality of nodes, wherein each node of the first plurality of nodes is formed outside every blockage of the plurality of blockages;
- and
- interconnecting the plurality of pins through nodes of the graph.
1 more element
A method of r outing an integrated circuit (IC) design, comprising:
- forming a first plurality of nodes for positioning objects of the IC design in a first layer, wherein at least two nodes of the first plurality of nodes are spaced apart by a first interval;
- and
- forming a second plurality of nodes for positioning objects of the IC design in a second layer, wherein at least two nodes of the second plurality of nodes are spaced apart by the first interval, and at least two nodes of the second plurality of nodes are spaced apart by one or more intervals greater than the first interval.
A method of routing an integrated circuit (IC) design, comprising:
- forming a first plurality of nodes for positioning objects of the IC design in a first layer, wherein at least two nodes of the first plurality of nodes are spaced apart by a first interval;
- and
- forming a second plurality of nodes for positioning objects of the IC design in a second layer, wherein at least two nodes of the second plurality of nodes are spaced apart by the first interval, and at least two nodes of the second plurality of nodes are spaced apart by one or more intervals less than the first interval.
A method of routing an integrated circuit (IC) design, comprising:
- forming a first plurality of nodes for positioning objects of the IC design in a first layer, wherein the first plurality of nodes includes a first plurality of common nodes and a first plurality of uncommon nodes;
- and
- forming a second plurality of nodes for positioning objects of the IC design in a second layer,
- wherein the second layer is at least substantially parallel to the first layer and the second layer is spaced apart from the first layer by about a layer distance along a layer axis,
- and wherein the second plurality of nodes includes a second plurality of common nodes, the first plurality of common nodes and the second plurality of common nodes share positions, such that if the second plurality of common nodes were shifted toward the first plurality of common nodes by about the layer distance along the layer axis, the first plurality of common nodes and the second plurality of common nodes would be substantially identical,
- and wherein if the second plurality of common nodes were shifted toward the first plurality of uncommon nodes by about the layer distance along the layer axis, no node of the first plurality of uncommon nodes and no node of the second plurality of common nodes would be substantially identical.
3 more elements
A method of routing an integrated circuit (IC) design, comprising:
- defining a volume of the IC design, wherein a subset of the volume carries wiring;
- and
- forming a plurality of nodes in the volume, wherein nodes of the plurality of nodes are limited to being formed within the subset of the volume.
A method of routing an integrated circuit (IC) design, comprising:
- accessing one or more routing pitches of one or more layers of the IC design;
- defining a volume of the IC design, wherein a subset of the volume carries wiring;
- forming a first plurality of nodes in the volume;
- and
- forming a second plurality of one or more nodes outside the volume, wherein at least one node of the second plurality of one or more nodes is formed at a pitch greater than at least one of the one or more routing pitches.
2 more elements
A method of routing an integrated circuit (IC) design, comprising:
- accessing a first cell instance of the IC design;
- accessing a second cell instance of the IC design adjacent to the first cell instance, wherein the first cell instance and the second cell instance are spaced apart by a channel;
- forming a first node near a first end of the channel;
- forming a second node near a second end of the channel;
- and
- connecting a wire directly between the first node and the second node.
3 more elements
A method of routing an integrated circuit (IC) design, comprising:
- accessing one or more routing pitches of one or more layers of the IC design;
- accessing a first cell instance of the integrated circuit design;
- accessing a second cell instance of the integrated circuit design adjacent to the first cell instance, wherein the first cell instance and the second cell instance are spaced apart by a channel;
- and
- forming a plurality of one or more nodes in the channel, wherein the plurality of one or more nodes in the channel has a pitch greater than at least one of the one or more routing pitches.
2 more elements
A method of routing an integrated circuit (IC) design, comprising:
- accessing the IC design including a plurality of objects;
- accessing a plurality of routing algorithms;
- interconnecting, with a first plurality of interconnections, one or more of the plurality of objects, at least partly in response to a first combination of one or more routing algorithms of the plurality of routing algorithms;
- storing the first plurality of interconnections;
- automatically determining a second combination of one or more routing algorithms;
- interconnecting, with a second plurality of interconnections, one or more of the plurality of objects, at least partly in response to the second combination of one or more routing algorithms of the plurality of routing algorithms;
- comparing results of the first plurality of interconnections and the second plurality of interconnections;
- and
- if results of the second plurality of interconnections are worse than results of the first plurality of interconnections, restoring the first plurality of interconnections.
6 more elements
A method of routing an integrated circuit (IC) design, comprising:
- interconnecting at least a first portion of the IC design at a first routing pitch;
- and
- if the interconnecting results in one or more design rule violations, routing at least a part of the first portion of the IC design at a second routing pitch less than the first routing pitch.
A method of routing an integrated circuit (IC) design, comprising:
- interconnecting at least a first part of the IC design on at least a first thread;
- and
- interconnecting at least a second part of the IC design on at least a second thread.
Dependencies are inferred from the claim text.