Integrated circuit comprising a memory cell of the DRAM type, and fabrication process
AssigneeSTMicroelectronics S.r.l.
InventorsOlivier Menut, Yvon Gris
Life of this patent
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Abstract
The integrated circuit comprises a semiconductor substrate SB supporting a memory cell PM of the DRAM type comprising an access transistor T and a storage capacitor TRC. The access transistor is made on the substrate, and the substrate includes a capacitive trench TRC buried beneath the transistor and forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor.
Claims20
A process for fabricating an integrated circuit comprising a semiconductor substrate supporting a memory cell of the DRAM type comprising an access transistor and a storage capacitor, wherein:
- a) an initial single-crystal substrate having locally a capacitive trench containing a polycrystalline fill material emerging at the surface of the initial substrate and forming a discontinuity in the crystal lattice is prepared;
- b) the initial substrate is recessed at the trench;
- c) the single-crystal lattice of the substrate around the periphery of the recess and the emergent part of the polycrystalline material for filling the trench are amorphized locally and so as to be self-aligned with respect to the trench;
- d) a layer of amorphous material having the same chemical composition as that of the initial substrate is deposited on the structure obtained in the previous step;
- e) the structure obtained in the previous step is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice of the initial substrate;
- and
- f) an upper substrate layer, in and on which the access transistor is made, is grown by epitaxy, the capacitive trench forming the storage capacitor being in contact with one of the source and drain regions of the transistor.
An integrated circuit comprising a semiconductor substrate supporting a memory cell of the DRAM type having an access transistor and a storage capacitor, and wherein the integrated circuit is obtained by the following fabrication process:
- a) an initial single-crystal substrate having locally a capacitive trench containing a polycrystalline fill material emerging at the surface of the initial substrate and forming a discontinuity in the crystal lattice is prepared;
- b) the initial substrate is recessed at the trench;
- c) the single-crystal lattice of the substrate around the periphery of the recess and the emergent part of the polycrystalline material for filling the trench are amorphized locally and so as to be self-aligned with respect to the trench;
- d) a layer of amorphous material having the same chemical composition as that of the initial substrate is deposited on the structure obtained in the previous step;
- e) the structure obtained in the previous step is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice of the initial substrate;
- and
- f) an upper substrate layer, in and on which the access transistor is made, is grown by epitaxy, the capacitive trench forming the storage capacitor being in contact with one of the source and drain regions of the transistor.
A memory comprising:
- at least one integrated circuit, each including a semiconductor substrate supporting a memory cell of the DRAM type having an access transistor and a storage capacitor, wherein the access transistor is made on the semiconductor substrate, and in that the semiconductor substrate comprises at least one buried capacitive trench under the transistor, forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor, and wherein the semiconductor substrate is made of silicon and in that the capacitive trench comprises an inner region of doped silicon partially enveloped by an isolating wall laterally separating the inner region of the substrate, and surmounted by an upper region of doped silicon, this upper region being in contact with the one of the source and drain regions of the transistor.
Dependencies are inferred from the claim text.