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AssigneeSTMicroelectronics S.r.I.
InventorsLivio Baldi, Alfonso Maurelli
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A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell. Between selectively etching the dielectric and depositing a second polysilicon layer, a first sub-step of removing the first gate oxide layer in the region for the logic transistor, and a second sub-step of growing a second oxide gate layer over the region, the second gate oxide layer having a different thickness than the first gate oxide layer.
A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor, the method comprising:
An integrated semiconductor device comprising at least one logic transistor and at least one nonvolatile floating gate memory cell, said memory cell comprising a first gate oxide layer over a silicon substrate, source and drain regions in said silicon substrate, a floating gate over said first gate oxide layer, a control gate superimposed on said floating gate, and a dielectric layer interposed between said floating gate and said control gate and electrically insulating said floating gate and said control gate, said logic transistor comprising a second gate oxide layer over said silicon substrate, a gate superimposed on said second gate oxide layer said second gate oxide layer has a different thickness than said first gate oxide layer.
A method of manufacturing an integrated circuit, comprising:
An integrated circuit device, comprising a logic transistor, a memory cell, and a high voltage transistor, the memory cell and the high voltage transistor each having a floating gate and a control gate, the floating gate comprising a first polysilicon layer formed on a first gate oxide, the control gate comprising a second polysilicon layer formed on a second gate oxide, the logic transistor having a gate comprising the second polysilicon layer formed on the second gate oxide, the second gate oxide having a thickness different than the thickness of the first gate oxide.
The device of claim 17 wherein the intermediate dielectric layer covers a top and sides of the first polysilicon layer.
Dependencies are inferred from the claim text.