Semiconductor device having silicon on insulator and fabricating method therefor

A method for fabricating a SOI semiconductor device comprising the steps of:

• forming a surface silicon layer on an insulating layer formed on a semiconductor substrate;
• forming an element isolating layer at predetermined portions of the surface silicon layer;
• forming a transistor on the surface silicon layer with a central gate electrode, gate spacers at lateral walls of the gate electrode, and source/drain regions formed in the surface silicon layer at both edges of the spacers;
• forming a groove by sequentially etching the element isolating layer and insulating layer of the surface silicon to expose predetermined portions of the semiconductor substrate;
• forming a diode diffusion region in a single junction structure of a high density impurity layer in the semiconductor substrate under the groove;
• forming groove spacers at lateral walls of the groove;
• and
• forming a self-aligned silicide layer on the diode diffusion region between the groove spacers.

A method for fabricating a SOI semiconductor device comprising the steps of:

• forming a surface silicon layer on an insulating layer formed on a first conductivity type semiconductor substrate;
• forming an element isolating layer at predetermined portions of the surface silicon layer;
• selectively ion-implanting a second conductivity impurity on a transistor portion to dope a predetermined internal portion of the surface silicon layer with a second conductivity type of impurity, and, at the same time, forming a second conductivity type of a well in the semiconductor substrate;
• forming a gate electrode by applying a gate insulating layer to the surface silicon layer doped with impurity;
• forming a groove by sequentially etching the element isolating layer and insulating layer of the surface silicon layer with a mask pattern that defines a diode portion, to expose a predetermined surface portion of the second conductivity type well at one side of the gate electrode;
• forming an LLD region in the surface silicon layer at both edges of the gate electrode by selectively ion-implanting a first conductivity type of a low density impurity at the transistor portion and forming a low density impurity layer in a second conductivity type of a well under the groove;
• forming spacers at both lateral walls of the gate electrode and at those of the groove;
• forming a source/drain region in the surface silicon layer at both edges of the gate electrode by selectively ion-implanting the first conductivity type of a high density impurity only to a transistor forming part and, then, forming a diode diffusion region constructed in a double junction structure, where the first conductivity type of a low density impurity layer surrounds the same type of a high density impurity layer, in the second conductivity type well under the groove;
• and
• forming a self-aligned silicide layer on the diode diffusion region between the surface exposed portion of the source/drain region having the gate electrode and the spacers.

A method for fabricating a SOI device comprising the steps of:

• forming a surface silicon layer on an insulating layer applied to a first conductivity type semiconductor substrate;
• forming an element isolating layer at a predetermined portion of the surface silicon layer;
• selectively ion-implanting a second conductivity impurity on a transistor portion to dope a predetermined internal portion of the surface silicon layer with a second conductivity type of impurity and, at the same time, forming a second conductivity type of a well in the semiconductor substrate;
• forming a gate electrode by inserting a gate insulating layer in the surface silicon layer doped with impurity;
• forming an LLD region in the surface silicon layer at both edges of the gate electrode by selectively ion-implanting a first conductivity type of a low density impurity at the transistor portion;
• forming first spacers at both lateral walls of the gate electrode;
• forming a groove by sequentially etching the element isolating layer and insulating layer of the surface silicon layer with a mask pattern that defines a diode forming portion, to expose a predetermined surface portion of the second conductivity type well at one side of the gate electrode;
• forming a source/drain region in the surface silicon layer at both edges of the gate electrode by selectively ion-implanting the first conductivity type of a high density impurity only at the transistor forming portion and, then, forming a single junction structure of the diode diffusion region in the second conductivity type well under the groove;
• forming second spacers at external sides of the first spacers at lateral walls of the groove;
• and
• forming a self-aligned silicide layer on the diode diffusion region between the surface exposed part of the source/drain region having the gate electrode and the second spacers.