US 2002/0118586 A1 · Integrated semiconductor memory device

Abstract

An integrated semiconductor memory device that can be subjected to a memory cell test in order to determine functional and defective memory cells includes addressable normal memory cells, a first redundancy unit having first addressable redundant memory cells and optically programmable switches for replacing an address of a defective normal memory cell by the address of a first redundant memory cell, and a second redundancy unit having second addressable redundant memory cells and electrically programmable switches for replacing an address of a defective normal memory cell by the address of a second redundant memory cell. The second redundancy unit can be connected by the activation of an irreversibly programmable switch, which enables a simplified functional test at the wafer level.

Claims11

Dependent claims

An integrated semiconductor memory device to be subjected to a memory cell test for determining functional and defective memory cells, comprising:

addressable memory cells;
a first redundancy unit having:
first addressable redundant memory cells;
and
optically programmable switches for replacing an address of a defective one of said memory cells by an address of one of said first redundant memory cells;
a second redundancy unit having:
second addressable redundant memory cells;
and
electrically programmable switches for replacing an address of a defective one of said memory cells by an address of one of said second redundant memory cells;
and
an irreversibly programmable switch connected to said second redundancy unit for activating said second redundancy unit.

8 more elements

Dependencies are inferred from the claim text.

Integrated semiconductor memory device

Life of this patent

Integrated semiconductor memory device

Life of this patent

Abstract

Claims11