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US 2002/0118584 A1Published application
Semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTeruhiko Amano
Life of this patent
Estimating the term…
Abstract
A row including a defective memory cell is replaced by a row of redundant memory cell, independently in each of a pair of memory blocks on opposing sides of a pair of row decoders 11. A redundancy determining circuit 1 for performing the replacement is provided for each memory block, and in the redundancy determining circuit 1, a plurality of fuse boxes 2 are arranged. Accordingly, as the fuses are laid-out in efficient manner, a semiconductor memory device is provided in which the circuits can be effectively arranged on the chip.
Claims11
A semiconductor memory device, comprising:
- a pair of row decoders;
- and
- a pair of memory blocks sandwiching said pair of row decoders therebetween, each of said pair of memory blocks including a plurality of normal memory cells arranged in a matrix of rows and columns and a plurality of redundant memory cells arranged at least in one row;
- and
- a redundancy determining circuit for replacing, independently in each of said pair of memory blocks, a row of said normal memory cells including a defective memory cell by a row of said redundant memory cells.
2 more elements
A semiconductor memory device, comprising:
- a plurality of pads;
- a circuit for generating a signal having a prescribed characteristic;
- and
- a fuse for tuning the characteristic of the signal generated by said circuit, arranged on an area between adjacent ones of said plurality of pads.
1 more element
Dependencies are inferred from the claim text.