Circuit and method for generating a variable frequency clock signal

A method of generating a clock signal having a variable frequency magnitude, comprising:

• generating a first signal having a substantially fixed-frequency magnitude;
• generating control signals based at least partially on the first signal;
• and
• generating the variable frequency magnitude clock signal in response to the control signals.

An astable oscillator circuit for generating a clock signal having a variable frequency magnitude, comprising:

• a first oscillator generating a first signal having a substantially fixed-frequency magnitude;
• a shift register coupled to receive the first signal on a serial input line and output a plurality of control bits on a plurality of parallel output lines based at least partially on the received first signal;
• and
• a plurality of variable delay circuits serially coupled one to another in a ring configuration and coupled to receive the control bits and generate the variable frequency magnitude clock signal in response to the received control bits.

A method of generating a clock signal having a variable frequency magnitude, comprising:

• generating a first signal having a substantially fixed-frequency magnitude;
• receiving the first signal on a serial input of a control circuit and outputting a plurality of control bits on a plurality of parallel output lines based at least partially on the first signal;
• and
• arbitrarily and selectively varying a delay of each of a plurality of first individual circuit elements that, in combination, generate the variable frequency magnitude signal, in response to the control bits.

An astable oscillator circuit for generating a clock signal having a variable frequency magnitude, comprising:

• a free-running ring oscillator generating a first signal having a substantially fixed-frequency magnitude that is less than the variable frequency magnitude;
• a linear feedback shift register coupled to receive the first signal on a serial input line and output a plurality of control bits on a plurality of parallel output lines based at least partially on the received first signal;
• and
• a plurality of variable delay circuits serially coupled one to another in a ring configuration and coupled to receive the control bits and generate the variable frequency magnitude clock signal in response to the received control bits, each of said plurality of variable delay circuits comprising:
• a plurality of inverting tristate drivers electrically connected in parallel with one another, and each including at least an input line, an output line, and an enable line,
• wherein at least one of said inverting tristate drivers has its enable line coupled to a potential that causes it to remain enabled, and a remainder of said inverting tristate drivers have their enable lines coupled to said plurality of parallel output lines.

A method of generating a clock signal having a variable frequency magnitude, comprising:

• generating a first signal having a substantially fixed-frequency magnitude that is less than the variable frequency magnitude;
• receiving the first signal on a serial input of a control circuit and outputting a plurality of substantially arbitrarily generated control bits on a plurality of parallel output lines based at least partially on the first signal;
• and
• arbitrarily and selectively varying a delay of each of a plurality of individual circuit elements that, in combination, generate the variable frequency magnitude signal in response to the control bits, by arbitrarily and selectively enabling parallel connected tristate drivers that comprise each of the individual circuit elements.

An astable oscillator circuit for generating a clock signal having a variable frequency magnitude, comprising:

• fixed-frequency oscillation means for generating a substantially fixed-frequency magnitude signal;
• control means for (i) receiving the substantially fixed-frequency magnitude signal and (ii) generating control signals based at least in part on the substantially fixed-frequency magnitude signal;
• and
• variable frequency oscillation means for (i) receiving the control signals and (ii) generating the variable frequency magnitude clock signal in response to the received control signals.