Phase frequency detector

A phase frequency detector comprising:

• a first flip-flop configured to receive a reference clock and to produce a first output;
• a second flip-flop configured to receive an internal clock and to produce a second output;
• and
• a reset circuit configured to receive the first output and the second output and to produce a reset signal which resets the first flip-flop and the second flip-flop, wherein the reset signal is activated when the first output and the second output are both logic high and remains activated until both the first output and the second output reach logic low.

A detector circuit comprising:

• means for generating a first signal to indicate that an internal clock is slower than a reference clock;
• means for generating a second signal to indicate that the internal clock is faster than the reference clock;
• and
• means for generating a reset signal to reset the first signal and the second signal, wherein the reset signal is activated when the first signal and the second signal are logic high and remains activated until the first signal and the second signal are logic low.

A method of performing phase frequency detection, said method comprising:

• generating a first differential signal which transitions from a first logic level to a second logic level based on the phase and frequency of a reference clock;
• generating a second differential signal which transitions from a first logic level to a second logic level based on the phase and frequency of a generated clock;
• and
• resetting the first differential signal and the second differential signal to the first logic level when both the first differential signal and the second differential signal are at the second logic level, wherein the resetting occurs until both the first differential signal and the second differential signal have transitioned to the first logic level;
• and
• comparing the first and second differential signals to generate a differential control voltage which drives a differential voltage controller oscillator.

A method of performing phase frequency detection, said method comprising:

• generating a first pulse which transitions from logic low to logic high at rising edges of a reference clock;
• generating a second pulse which transitions from logic low to logic high at rising edges of a generated clock;
• and
• resetting the first pulse and the second pulse to logic low when both the first pulse and the second pulse are logic high, wherein the resetting occurs until both the first pulse and the second pulse have transitioned to logic low.