Semiconductor integrated circuit device and wiring arranging method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsShinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa, Toshikazu Sei
Life of this patent
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Abstract
Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
Claims3
A semiconductor integrated circuit device, comprising:
- a plurality of I/O slots arranged in parallel along the peripheral portion of a chip within the inner region of the chip and having input/output cells connected thereto;
- a plurality of pads arranged a predetermined distance apart from each other above said I/O slot and extending from the peripheral portion of the chip toward the central portion;
- a plurality of first wiring each having one end positioned in said pad and having the other end positioned in the peripheral region of the inner portion of the chip above the I/O slot;
- and
- a second wiring arranged in the outermost peripheral region of the chip and serving to connect the other end of each of the plural the first wiring to a predetermined I/O slot.
A method of connecting the wiring of a semiconductor integrated circuit device for connecting a plurality of I/O slots arranged in parallel along the peripheral portion of a chip within the inner region of the chip and having input/output cells connected thereto to a plurality of pads arranged a predetermined distance apart from each other above said I/O slot and extending from the peripheral portion of the chip toward the central portion, comprising the steps of:
- connecting each of said pads to the peripheral portion above the I/O slot in the inner region of the chip;
- and
- connecting the peripheral portion in the inner region of the chip to a desired I/O slot in the outermost peripheral region of the chip.
Dependencies are inferred from the claim text.