High bandwidth 3d memory packaging technique

A three-dimensional array of modules comprising in combination:

• a plurality of pedestal connectors;
• each of said pedestal connectors comprised of a conductor core and a plane extending from said conductor core;
• each of said pedestal connectors having an input grid array on a lower surface of said conductor core and a corresponding output grid array on an upper surface of said conductor core;
• said plurality of pedestal connectors stacked one on top of another with the output grid array of one pedestal connector connected to the input grid array of the next pedestal connector;
• conductive paths formed in each pedestal connector between its input grid array and its output grid array;
• said conductive paths skewed from input grid array to output grid array to form a plurality of unique paths from the input grid of the lowest pedestal connector in the stack to respective branch conductive paths extending into said plane.