US 2002/0117730 A1 · Semiconductor device

Abstract

An object of the present invention is to provide a semiconductor device, which is able to provide a desired output voltage of the ECM without signal loss caused by parasitic capacitances. A semiconductor device comprises a semiconductor substrate; integrated network elements including an input transistor being integrated on the semiconductor substrate, the input transistor having an input terminal; a first bonding pad connected to the input terminal of the input transistor for testing properties of the input transistor; a second bonding pad connected to one of the integrated network elements for external connection; and a surface area of the first bonding pad being smaller than that of the second bonding pad.

Claims7

Dependent claims

A semiconductor device comprising:

a semiconductor substrate;
integrated network elements including an input transistor being integrated on the semiconductor substrate, the input transistor having an input terminal;
a first bonding pad connected to the input terminal of the input transistor for testing properties of the input transistor;
a second bonding pad connected to one of the integrated network elements for external connection;
and
a surface area of the first bonding pad being smaller than that of the second bonding pad.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/119,711Filed 11 Apr 2002

Priority

JP 83782/199926 Mar 1999

Published

29 Aug 2002

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 84/403
Combinations of FETs or IGBTs with BJTs: combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
H10D 84/87
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs: of PN-junction…
H10P 74/273
Structural arrangements therefor: interconnections for measuring or testing, e.g. probe pads
H10W 10/031
Manufacture or treatment: of isolation regions comprising PN junctions

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims7