Method of fabricating a MOS capacitor

A method of fabricating a metal-oxide semiconductor (MOS) capacitor, comprising:

• providing a doped region in a substrate with a dopant conductive type;
• forming a gate oxide layer on the substrate;
• forming a gate on the gate oxide layer at the doped region;
• forming a source/drain region in the doped region at a side of the gate, wherein the source/drain region is doped with dopants having the same dopant conductive type of the doped region;
• and
• performing a channel implantation to form a channel implantation region in the doped region under the gate abutting the source/drain region, wherein the channel implantation region is implanted with the same dopant conductive type of the doped region.

A method of fabricating a metal-oxide semiconductor (MOS) capacitor in a complementary MOS (CMOS) fabrication process with dual-doped electrodes, the method comprising:

• providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type;
• forming a first MOS capacitor on the first well, wherein the first MOS capacitor comprises a first gate oxide layer on the first well, a first gate layer of the first conductive type on the first gate oxide layer serving as a first gate electrode, a first doped region of the first conductive type in the first well at each side of the first gate layer, and a first channel implantation region of the first conductive type under the first gate oxide layer abutting the first doped region, wherein the first doped region serves as a first substrate electrode;
• and
• forming a second MOS capacitor on the second well, wherein the second MOS capacitor comprises a second gate oxide layer on the second well, a second gate layer of the second conductive type on the second gate oxide layer serving as a second gate electrode, a second doped region of the second conductive type in the second well at each side of the second gate layer, and a second channel implantation region of the second conductive type under the second gate oxide layer abutting the second doped region, wherein the second doped region serves as a second substrate electrode.

A metal-oxide semiconductor (MOS) capacitor in a complementary MOS (CMOS) device, the MOS capacitor comprising:

• a substrate of a first conductive type, having a first well of the first conductive type and a second well of a second conductive type;
• a first MOS capacitor of the first conductive type formed on the substrate at the first well, wherein the first MOS capacitor comprises:
• a first substrate electrode of the first conductive type in the first well;
• a first dielectric layer on the first substrate electrode;
• and
• a first gate electrode of the first conductive type on the first gate oxide layer;
• and
• a second MOS capacitor of the second conductive type formed on the substrate at the second well, wherein the second MOS capacitor comprises:
• a second substrate electrode of the first conductive type in the second well;
• a second dielectric layer on the second substrate electrode;
• and
• a second gate electrode of the second conductive type on the second gate oxide layer.

In combination with a dual-poly complementary metal-oxide semiconductor (CMOS) integrated circuit, wherein the CMOS integrated circuit has an NMOS transistor with an N-type gate electrode and an N-type source/drain electrode on a P-type substrate or a P-type well, and has a PMOS transistor with a P-type gate electrode and a source/drain electrode on an N-type substrate or an N-type well, the improvement which comprises:

• at least one MOS capacitor selected from a group consisting of:
• an NMOS capacitor on an N-type doped region, having an N-type junction electrode in the N-type doped region, a first gate dielectric layer on the N-type doped region, and an N-type gate electrode on the first dielectric layer;
• and
• a PMOS capacitor on a P-type doped region, having a P-type junction electrode in the P-type doped region, a second gate dielectric layer on the P-type doped region, and a P-type gate electrode on the second dielectric layer.

A layout of a complementary metal-oxide semiconductor (CMOS) circuit, having a P-well implantation mask, an N-well implantation mask, an active region forming mask, a gate forming mask, an N-type implantation mask, and a P-type implantation mask, whereby an NMOS transistor and a PMOS transistor are respectively formed on a P-type dope region and an N-type doped region in the CMOS circuit, the improvement of the layout which comprises:

• using the same masks but different implantation types arranged to form at least one MOS capacitor selected from a group consisting of
• an NMOS capacitor in an N-type dope region of a substrate, comprising an N-FILE:
• type active region with an N-type gate electrode thereon, and an N-type junction electrode beside the N-type gate electrode, and
• a PMOS capacitor in a P-type dope region of the substrate, comprising a P-type active region with a P-type gate electrode thereon, and a P-type junction electrode beside the P-type gate electrode.